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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpMul.v] - Blame information for rev 69

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpMul.v
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//              - floating point multiplier
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//              - two cycle latency
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//              - can issue every clock cycle
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//              - parameterized FPWIDth
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//              - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      Floating Point Multiplier / Divider
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//
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//      This multiplier/divider handles denormalized numbers.
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//      The output format is of an internal expanded representation
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//      in preparation to be fed into a normalization unit, then
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//      rounding. Basically, it's the same as the regular format
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//      except the mantissa is doubled in size, the leading two
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//      bits of which are assumed to be whole bits.
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//
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//
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//      Floating Point Multiplier
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//
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//      Properties:
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//      +-inf * +-inf = -+inf   (this is handled by exOver)
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//      +-inf * 0     = QNaN
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//      
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//      1 sign number
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//      8 exponent
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//      48 mantissa
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//
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// ============================================================================
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`include "fpConfig.sv"
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module fpMul (clk, ce, a, b, o, sign_exe, inf, overflow, underflow);
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parameter FPWID = 32;
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`include "fpSize.sv"
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input clk;
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input ce;
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input  [MSB:0] a, b;
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output [EX:0] o;
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output sign_exe;
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output inf;
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output overflow;
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output underflow;
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reg [EMSB:0] xo1;                // extra bit for sign
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reg [FX:0] mo1;
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// constants
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wire [EMSB:0] infXp = {EMSB+1{1'b1}};    // infinite / NaN - all ones
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// The following is the value for an exponent of zero, with the offset
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// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
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wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}};        //2^0 exponent
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// The following is a template for a quiet nan. (MSB=1)
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wire [FMSB:0] qNaN  = {1'b1,{FMSB{1'b0}}};
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// variables
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reg [FX:0] fract1,fract1a;
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wire [FX:0] fracto;
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wire [EMSB+2:0] ex1;     // sum of exponents
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wire [EMSB  :0] ex2;
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// Decompose the operands
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wire sa, sb;                    // sign bit
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wire [EMSB:0] xa, xb;    // exponent bits
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wire [FMSB+1:0] fracta, fractb;
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wire a_dn, b_dn;                        // a/b is denormalized
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wire aNan, bNan, aNan1, bNan1;
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wire az, bz;
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wire aInf, bInf, aInf1, bInf1;
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// -----------------------------------------------------------
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// First clock
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// - decode the input operands
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// - derive basic information
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// - calculate exponent
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// - calculate fraction
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// -----------------------------------------------------------
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fpDecomp #(FPWID) u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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fpDecomp #(FPWID) u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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// Compute the sum of the exponents.
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// correct the exponent for denormalized operands
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// adjust the sum by the exponent offset (subtract 127)
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// mul: ex1 = xa + xb,  result should always be < 1ffh
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assign ex1 = (az|bz) ? 0 : (xa|a_dn) + (xb|b_dn) - bias;
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generate
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if (FPWID+`EXTRA_BITS==80) begin
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reg [31:0] p00,p01,p02,p03;
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reg [31:0] p10,p11,p12,p13;
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reg [31:0] p20,p21,p22,p23;
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reg [31:0] p30,p31,p32,p33;
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        always @(posedge clk)
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        if (ce) begin
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                p00 <= fracta[15: 0] * fractb[15: 0];
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                p01 <= fracta[31:16] * fractb[15: 0];
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                p02 <= fracta[47:32] * fractb[15: 0];
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                p03 <= fracta[63:48] * fractb[15: 0];
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                p10 <= fracta[15: 0] * fractb[31:16];
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                p11 <= fracta[31:16] * fractb[31:16];
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                p12 <= fracta[47:32] * fractb[31:16];
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                p13 <= fracta[63:48] * fractb[31:16];
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                p20 <= fracta[15: 0] * fractb[47:32];
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                p21 <= fracta[31:16] * fractb[47:32];
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                p22 <= fracta[47:32] * fractb[47:32];
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                p23 <= fracta[63:48] * fractb[47:32];
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                p30 <= fracta[15: 0] * fractb[63:48];
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                p31 <= fracta[31:16] * fractb[63:48];
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                p32 <= fracta[47:32] * fractb[63:48];
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                p33 <= fracta[63:48] * fractb[63:48];
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                fract1 <=                                               {p03,48'b0} + {p02,32'b0} + {p01,16'b0} + p00 +
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                                                                  {p13,64'b0} + {p12,48'b0} + {p11,32'b0} + {p10,16'b0} +
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                                        {p23,80'b0} + {p22,64'b0} + {p21,48'b0} + {p20,32'b0} +
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      {p33,96'b0} + {p32,80'b0} + {p31,64'b0} + {p30,48'b0}
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                                ;
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        end
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end
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else if (FPWID+`EXTRA_BITS==64) begin
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reg [35:0] p00,p01,p02;
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reg [35:0] p10,p11,p12;
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reg [35:0] p20,p21,p22;
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        always @(posedge clk)
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        if (ce) begin
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                p00 <= fracta[17: 0] * fractb[17: 0];
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                p01 <= fracta[35:18] * fractb[17: 0];
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                p02 <= fracta[52:36] * fractb[17: 0];
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                p10 <= fracta[17: 0] * fractb[35:18];
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                p11 <= fracta[35:18] * fractb[35:18];
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                p12 <= fracta[52:36] * fractb[35:18];
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                p20 <= fracta[17: 0] * fractb[52:36];
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                p21 <= fracta[35:18] * fractb[52:36];
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                p22 <= fracta[52:36] * fractb[52:36];
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                fract1 <=                                   {p02,36'b0} + {p01,18'b0} + p00 +
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                                                                  {p12,54'b0} + {p11,36'b0} + {p10,18'b0} +
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                                        {p22,72'b0} + {p21,54'b0} + {p20,36'b0}
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                                ;
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        end
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end
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else if (FPWID+`EXTRA_BITS==32) begin
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reg [23:0] p00,p01,p02;
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reg [23:0] p10,p11,p12;
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reg [23:0] p20,p21,p22;
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        always @(posedge clk)
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        if (ce) begin
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                p00 <= fracta[11: 0] * fractb[11: 0];
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                p01 <= fracta[23:12] * fractb[11: 0];
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                p10 <= fracta[11: 0] * fractb[23:12];
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                p11 <= fracta[23:12] * fractb[23:12];
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                fract1 <= {p11,p00} + {p01,12'b0} + {p10,12'b0};
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        end
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end
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else begin
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        always @(posedge clk)
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    if (ce) begin
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        fract1a <= fracta * fractb;
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        fract1 <= fract1a;
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    end
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end
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endgenerate
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// Status
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wire under1, over1;
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wire under = ex1[EMSB+2];       // exponent underflow
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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delay2 #(EMSB+1) u3 (.clk(clk), .ce(ce), .i(ex1[EMSB:0]), .o(ex2) );
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delay2 u2a (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
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delay2 u2b (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
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delay2 u6  (.clk(clk), .ce(ce), .i(under), .o(under1) );
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delay2 u7  (.clk(clk), .ce(ce), .i(over), .o(over1) );
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// determine when a NaN is output
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wire qNaNOut;
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wire [FPWID-1:0] a1,b1;
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delay2 u5 (.clk(clk), .ce(ce), .i((aInf&bz)|(bInf&az)), .o(qNaNOut) );
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delay2 u14 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
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delay2 u15 (.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
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delay2 #(FPWID) u16 (.clk(clk), .ce(ce), .i(a), .o(a1) );
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delay2 #(FPWID) u17 (.clk(clk), .ce(ce), .i(b), .o(b1) );
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// -----------------------------------------------------------
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// Second clock
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// - correct xponent and mantissa for exceptional conditions
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// -----------------------------------------------------------
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wire so1;
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delay3 u8 (.clk(clk), .ce(ce), .i(sa ^ sb), .o(so1) );// two clock delay!
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always @(posedge clk)
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        if (ce)
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                casez({qNaNOut|aNan1|bNan1,aInf1,bInf1,over1,under1})
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                5'b1????:       xo1 = infXp;    // qNaN - infinity * zero
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                5'b01???:       xo1 = infXp;    // 'a' infinite
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                5'b001??:       xo1 = infXp;    // 'b' infinite
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                5'b0001?:       xo1 = infXp;    // result overflow
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                5'b00001:       xo1 = ex2[EMSB:0];//0;           // underflow
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                default:        xo1 = ex2[EMSB:0];       // situation normal
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                endcase
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always @(posedge clk)
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        if (ce)
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                casez({aNan1,bNan1,qNaNOut,aInf1,bInf1,over1})
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                6'b1?????:  mo1 = {1'b1,1'b1,a1[FMSB-1:0],{FMSB+1{1'b0}}};
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    6'b01????:  mo1 = {1'b1,1'b1,b1[FMSB-1:0],{FMSB+1{1'b0}}};
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                6'b001???:      mo1 = {1'b1,qNaN|3'd4,{FMSB+1{1'b0}}};  // multiply inf * zero
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                6'b0001??:      mo1 = 0; // mul inf's
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                6'b00001?:      mo1 = 0; // mul inf's
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                6'b000001:      mo1 = 0; // mul overflow
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                default:        mo1 = fract1;
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                endcase
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delay3 u10 (.clk(clk), .ce(ce), .i(sa & sb), .o(sign_exe) );
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delay1 u11 (.clk(clk), .ce(ce), .i(over1),  .o(overflow) );
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delay1 u12 (.clk(clk), .ce(ce), .i(over1),  .o(inf) );
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delay1 u13 (.clk(clk), .ce(ce), .i(under1), .o(underflow) );
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assign o = {so1,xo1,mo1};
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endmodule
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// Multiplier with normalization and rounding.
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module fpMulnr(clk, ce, a, b, o, rm, sign_exe, inf, overflow, underflow);
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parameter FPWID=32;
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`include "fpSize.sv"
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input clk;
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input ce;
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input  [MSB:0] a, b;
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output [MSB:0] o;
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input [2:0] rm;
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output sign_exe;
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output inf;
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output overflow;
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output underflow;
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wire [EX:0] o1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [MSB+3:0] fpn0;
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fpMul       #(FPWID) u1 (clk, ce, a, b, o1, sign_exe1, inf1, overflow1, underflow1);
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fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
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fpRoundReg  #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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endmodule
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