OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpNextAfter.sv] - Blame information for rev 84

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      fpNextAfter.v
9
//              - floating point nextafter()
10
//              - return next representable value
11
//
12
// This source file is free software: you can redistribute it and/or modify
13
// it under the terms of the GNU Lesser General Public License as published
14
// by the Free Software Foundation, either version 3 of the License, or
15
// (at your option) any later version.
16
//
17
// This source file is distributed in the hope that it will be useful,
18
// but WITHOUT ANY WARRANTY; without even the implied warranty of
19
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20
// GNU General Public License for more details.
21
//
22
// You should have received a copy of the GNU General Public License
23
// along with this program.  If not, see .
24
//
25
// ============================================================================
26
 
27
`include "fpConfig.sv"
28
 
29
module fpNextAfter(clk, ce, a, b, o);
30
parameter FPWID=80;
31
`include "fpSize.sv"
32
input clk;
33
input ce;
34
input [MSB:0] a;
35
input [MSB:0] b;
36
output reg [MSB:0] o;
37
 
38
wire [4:0] cmp_o;
39
wire nana, nanb;
40
wire xza, mza;
41
 
42
fpCompare #(FPWID) u1 (.a(a), .b(b), .o(cmp_o), .nanx(nanxab) );
43
fpDecomp #(FPWID) u2 (.i(a), .sgn(), .exp(), .man(), .fract(), .xz(xza), .mz(mza), .vz(), .inf(), .xinf(), .qnan(), .snan(), .nan(nana));
44
fpDecomp #(FPWID) u3 (.i(b), .sgn(), .exp(), .man(), .fract(), .xz(), .mz(), .vz(), .inf(), .xinf(), .qnan(), .snan(), .nan(nanb));
45
wire [MSB:0] ap1 = a + {2'd1,{`EXTRA_BITS{1'b0}}};
46
wire [MSB:0] am1 = a - {2'd1,{`EXTRA_BITS{1'b0}}};
47
wire [EMSB:0] infXp = {EMSB+1{1'b1}};
48
 
49
always  @(posedge clk)
50
if (ce)
51
        casez({a[MSB],cmp_o})
52
        6'b?1????:      o <= nana ? a : b;      // Unordered
53
        6'b????1?:      o <= a;                                                 // a,b Equal
54
        6'b0????1:
55
                if (ap1[MSB-1:FMSB+1]==infXp)
56
                        o <= {a[MSB:FMSB+1],{FMSB+1{1'b0}}};
57
                else
58
                        o <= ap1;
59
        6'b0????0:
60
                if (xza && mza)
61
                        ;
62
                else
63
                        o <= am1;
64
        6'b1????0:
65
                if (ap1[MSB-1:FMSB+1]==infXp)
66
                        o <= {a[MSB:FMSB+1],{FMSB+1{1'b0}}};
67
                else
68
                        o <= ap1;
69
        6'b1????1:
70
                if (xza && mza)
71
                        ;
72
                else
73
                        o <= am1;
74
        default:        o <= a;
75
        endcase
76
 
77
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.