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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpNormalize.sv] - Blame information for rev 48

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1 48 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      fpNormalize.sv
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//    - floating point normalization unit
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//    - eight cycle latency
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//    - parameterized width
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//    - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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//      This unit takes a floating point number in an intermediate
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// format and normalizes it. No normalization occurs
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// for NaN's or infinities. The unit has a two cycle latency.
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//
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// The mantissa is assumed to start with two whole bits on
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// the left. The remaining bits are fractional.
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//
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// The width of the incoming format is reduced via a generation
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// of sticky bit in place of the low order fractional bits.
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//
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// On an underflowed input, the incoming exponent is assumed
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// to be negative. A right shift is needed.
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// ============================================================================
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import fp::*;
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module fpNormalize(clk, ce, i, o, under_i, under_o, inexact_o);
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input clk;
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input ce;
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input [EX:0] i;         // expanded format input
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output [MSB+3:0] o;             // normalized output + guard, sticky and round bits, + 1 whole digit
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input under_i;
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output under_o;
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output inexact_o;
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// ----------------------------------------------------------------------------
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// No Clock required
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// ----------------------------------------------------------------------------
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reg [EMSB:0] xo0;
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reg so0;
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always @*
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        xo0 <= i[EX-1:FX+1];
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always @*
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        so0 <= i[EX];           // sign doesn't change
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// ----------------------------------------------------------------------------
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// Clock #1
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// - Capture exponent information
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// ----------------------------------------------------------------------------
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reg xInf1a, xInf1b, xInf1c;
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wire [FX:0] i1;
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delay1 #(FX+1) u11 (.clk(clk), .ce(ce), .i(i), .o(i1));
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always @(posedge clk)
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        if (ce) xInf1a <= &xo0 & !under_i;
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always @(posedge clk)
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        if (ce) xInf1b <= &xo0[EMSB:1] & !under_i;
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always @(posedge clk)
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        if (ce) xInf1c = &xo0;
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// ----------------------------------------------------------------------------
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// Clock #2
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// - determine exponent increment
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// Since the there are *three* whole digits in the incoming format
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// the number of whole digits needs to be reduced. If the MSB is
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// set, then increment the exponent and no shift is needed.
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// ----------------------------------------------------------------------------
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wire xInf2c, xInf2b;
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wire [EMSB:0] xo2;
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reg incExpByOne2, incExpByTwo2;
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delay1 u21 (.clk(clk), .ce(ce), .i(xInf1c), .o(xInf2c));
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delay1 u22 (.clk(clk), .ce(ce), .i(xInf1b), .o(xInf2b));
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delay2 #(EMSB+1) u23 (.clk(clk), .ce(ce), .i(xo0), .o(xo2));
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delay2 u24 (.clk(clk), .ce(ce), .i(under_i), .o(under2));
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always @(posedge clk)
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        if (ce) incExpByTwo2 <= !xInf1b & i1[FX];
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always @(posedge clk)
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        if (ce) incExpByOne2 <= !xInf1a & i1[FX-1];
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// ----------------------------------------------------------------------------
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// Clock #3
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// - increment exponent
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// - detect a zero mantissa
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// ----------------------------------------------------------------------------
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wire incExpByTwo3;
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wire incExpByOne3;
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wire [FX:0] i3;
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reg [EMSB:0] xo3;
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reg zeroMan3;
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delay1 u31 (.clk(clk), .ce(ce), .i(incExpByTwo2), .o(incExpByTwo3));
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delay1 u32 (.clk(clk), .ce(ce), .i(incExpByOne2), .o(incExpByOne3));
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delay3 #(FX+1) u33 (.clk(clk), .ce(ce), .i(i[FX:0]), .o(i3));
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wire [EMSB+1:0] xv3a = xo2 + {incExpByTwo2,1'b0};
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wire [EMSB+1:0] xv3b = xo2 + incExpByOne2;
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always @(posedge clk)
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        if (ce) xo3 <= xo2 + (incExpByTwo2 ? 2'd2 : incExpByOne2 ? 2'd1 : 2'd0);
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always @(posedge clk)
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        if(ce) zeroMan3 <= ((xv3b[EMSB+1]|| &xv3b[EMSB:0])||(xv3a[EMSB+1]| &xv3a[EMSB:0]))
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                                                                                         && !under2 && !xInf2c;
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// ----------------------------------------------------------------------------
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// Clock #4
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// - Shift mantissa left
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// - If infinity is reached then set the mantissa to zero
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//   shift mantissa left to reduce to a single whole digit
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// - create sticky bit
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// ----------------------------------------------------------------------------
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reg [FMSB+4:0] mo4;
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reg inexact4;
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always @(posedge clk)
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if(ce)
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casez({zeroMan3,incExpByTwo3,incExpByOne3})
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3'b1??: mo4 <= 1'd0;
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3'b01?: mo4 <= {i3[FX:FMSB+1],|i3[FMSB:0]};
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3'b001: mo4 <= {i3[FX-1:FMSB],|i3[FMSB-1:0]};
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default:        mo4 <= {i3[FX-2:FMSB-1],|i3[FMSB-2:0]};
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endcase
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always @(posedge clk)
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if(ce)
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casez({zeroMan3,incExpByTwo3,incExpByOne3})
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3'b1??: inexact4 <= 1'd0;
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3'b01?: inexact4 <= |i3[FMSB:0];
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3'b001: inexact4 <= |i3[FMSB-1:0];
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default:        inexact4 <= |i3[FMSB-2:0];
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endcase
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// ----------------------------------------------------------------------------
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// Clock edge #5
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// - count leading zeros
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// ----------------------------------------------------------------------------
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wire [7:0] leadingZeros5;
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wire [EMSB:0] xo5;
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wire xInf5;
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delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
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delay3 #(1)      u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
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generate
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begin
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if (FPWID <= 32) begin
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) );
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assign leadingZeros5[7:6] = 2'b00;
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end
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else if (FPWID<=64) begin
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assign leadingZeros5[7] = 1'b0;
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) );
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end
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else if (FPWID<=80) begin
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assign leadingZeros5[7] = 1'b0;
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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else if (FPWID<=84) begin
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) );
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end
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else if (FPWID<=96) begin
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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else if (FPWID<=128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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endgenerate
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// ----------------------------------------------------------------------------
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// Clock edge #6
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// - Compute how much we want to decrement exponent by
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// - compute amount to shift left and right
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// - at infinity the exponent can't be incremented, so we can't shift right
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//   otherwise it was an underflow situation so the exponent was negative
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//   shift amount needs to be negated for shift register
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// If the exponent underflowed, then the shift direction must be to the
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// right regardless of mantissa bits; the number is denormalized.
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// Otherwise the shift direction must be to the left.
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// ----------------------------------------------------------------------------
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reg [7:0] lshiftAmt6;
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reg [7:0] rshiftAmt6;
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wire rightOrLeft6;      // 0=left,1=right
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wire xInf6;
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wire [EMSB:0] xo6;
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wire [FMSB+4:0] mo6;
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wire zeroMan6;
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vtdl #(1) u61 (.clk(clk), .ce(ce), .a(4'd5), .d(under_i), .q(rightOrLeft6) );
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delay1 #(EMSB+1) u62 (.clk(clk), .ce(ce), .i(xo5), .o(xo6));
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delay2 #(FMSB+5) u63 (.clk(clk), .ce(ce), .i(mo4), .o(mo6) );
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delay1 #(1)      u64 (.clk(clk), .ce(ce), .i(xInf5), .o(xInf6) );
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delay3 u65 (.clk(clk), .ce(ce),  .i(zeroMan3), .o(zeroMan6));
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always @(posedge clk)
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        if (ce) lshiftAmt6 <= leadingZeros5 > xo5 ? xo5 : leadingZeros5;
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always @(posedge clk)
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        if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1;    // xo2 is negative !
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// ----------------------------------------------------------------------------
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// Clock edge #7
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// - fogure exponent
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// - shift mantissa
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// ----------------------------------------------------------------------------
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reg [EMSB:0] xo7;
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wire rightOrLeft7;
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reg [FMSB+4:0] mo7l, mo7r;
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delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
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always @(posedge clk)
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if (ce)
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        xo7 <= zeroMan6 ? xo6 :
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                xInf6 ? xo6 :                                   // an infinite exponent is either a NaN or infinity; no need to change
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                rightOrLeft6 ? 1'd0 :   // on a right shift, the exponent was negative, it's being made to zero
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                xo6 - lshiftAmt6;                       // on a left shift, the exponent can't be decremented below zero
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always @(posedge clk)
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        if (ce) mo7r <= mo6 >> rshiftAmt6;
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always @(posedge clk)
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        if (ce) mo7l <= mo6 << lshiftAmt6;
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// ----------------------------------------------------------------------------
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// Clock edge #8
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// - select mantissa
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// ----------------------------------------------------------------------------
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wire so;
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wire [EMSB:0] xo;
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reg [FMSB+4:0] mo;
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vtdl #(1) u81 (.clk(clk), .ce(ce), .a(4'd7), .d(so0), .q(so) );
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delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
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vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
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delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
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always @(posedge clk)
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        if (ce) mo <= rightOrLeft7 ? mo7r : mo7l;
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assign o = {so,xo,mo[FMSB+4:1]};
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endmodule
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