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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpScaleb.sv] - Blame information for rev 69

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      fpScaleb.sv
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//              - floating point Scaleb()
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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module fpScaleb(clk, ce, a, b, o);
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parameter FPWID=80;
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`include "fpSize.sv"
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input clk;
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input ce;
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input [FPWID-1+`EXTRA_BITS:0] a;
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input [FPWID-1+`EXTRA_BITS:0] b;
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output reg [FPWID-1+`EXTRA_BITS:0] o;
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wire [4:0] cmp_o;
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wire nana, nanb;
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wire xza, mza;
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wire [EMSB:0] infXp = {EMSB+1{1'b1}};
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wire [EMSB:0] xa;
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wire xinfa;
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wire anan;
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reg anan1;
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wire sa;
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reg sa1, sa2;
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wire [FMSB:0] ma;
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reg [EMSB+1:0] xa1a, xa1b, xa2;
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reg [FMSB:0] ma1, ma2;
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wire bs = b[FPWID-1];
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reg bs1;
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fpDecomp #(FPWID) u1 (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(), .xz(xza), .mz(), .vz(), .inf(), .xinf(xinfa), .qnan(), .snan(), .nan(anan));
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// ----------------------------------------------------------------------------
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// Clock cycle 1
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// ----------------------------------------------------------------------------
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always @(posedge clk)
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        if (ce) xa1a <= xa;
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always @(posedge clk)
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        if (ce) xa1b <= xa + b;
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always @(posedge clk)
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        if (ce) bs1 <= bs;
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always @(posedge clk)
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        if (ce) anan1 <= anan;
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always @(posedge clk)
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        if (ce) sa1 <= sa;
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always @(posedge clk)
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        if (ce) ma1 <= ma;
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// ----------------------------------------------------------------------------
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// Clock cycle 2
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// ----------------------------------------------------------------------------
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always @(posedge clk)
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        if (ce) sa2 <= sa1;
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always @(posedge clk)
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if (ce) begin
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        if (anan1) begin
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                xa2 <= xa1a;
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                ma2 <= ma1;
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        end
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        // Underflow? -> limit exponent to zero
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        else if (bs1 & xa1b[EMSB+1]) begin
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                xa2 <= 1'd0;
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                ma2 <= ma1;
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        end
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        // overflow ? -> set value to infinity
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        else if (~bs1 & xa1b[EMSB+1]) begin
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                xa2 <= infXp;
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                ma2 <= 1'd0;
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        end
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        else begin
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                xa2 <= xa1b;
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                ma2 <= ma1;
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        end
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end
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assign o = {sa2,xa2,ma2};
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endmodule

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