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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpSigmoid.v] - Blame information for rev 88

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2017-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      sigmoid.v
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//              - perform sigmoid function
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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// This module returns the sigmoid of a number using a lookup table.
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// -1.0 or +1.0 is returned for entries outside of the range -8.0 to +8.0
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//                                                                          
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// ToTo: check pipelining of values
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// ============================================================================
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`include "fpConfig.sv"
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`define ONE80                                   80'h3FFF0000000000000000
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`define EIGHT80                         80'h40020000000000000000
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`define FIVETWELVE80    80'h40080000000000000000
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`define ONE64                                   64'h3FF0000000000000
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`define EIGHT64                         64'h4020000000000000
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`define FIVETWELVE64    64'h4080000000000000
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`define ONE40                                   40'h3FE0000000
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`define EIGHT40                         40'h4040000000
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`define ONE32                                   32'h7F000000
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`define EIGHT32                         32'h42000000
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`define FIVETWELVE32    32'h48000000
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module fpSigmoid(clk, ce, a, o);
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parameter FPWID = 128;
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`include "fpSize.sv"
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input clk;
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input ce;
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input [MSB:0] a;
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output reg [MSB:0] o;
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wire [4:0] cmp1_o;
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reg [4:0] cmp2_o;
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// Just the mantissa is stored in the table to economize on the storate.
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// The exponent is always the same value (0x3ff). Only the top 32 bits of
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// the mantissa are stored.
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(* ram_style="block" *)
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reg [31:0] SigmoidLUT [0:1023];
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// Check if the input is in the range (-8 to +8)
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// We take the absolute value by trimming off the sign bit.
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generate begin : ext
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if (FPWID+`EXTRA_BITS==80)
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fp_cmp_unit #(FPWID) u1 (.a(a & 80'h7FFFFFFFFFFFFFFFFFFF), .b(`EIGHT80), .o(cmp1_o), .nanx() );
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else if (FPWID+`EXTRA_BITS==64)
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fp_cmp_unit #(FPWID) u1 (.a(a & 64'h7FFFFFFFFFFFFFFF), .b(`EIGHT64), .o(cmp1_o), .nanx() );
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else if (FPWID+`EXTRA_BITS==40)
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fp_cmp_unit #(FPWID) u1 (.a(a & 40'h7FFFFFFFFF), .b(`EIGHT40), .o(cmp1_o), .nanx() );
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else if (FPWID+`EXTRA_BITS==32)
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fp_cmp_unit #(FPWID) u1 (.a(a & 32'h7FFFFFFF), .b(`EIGHT32), .o(cmp1_o), .nanx() );
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else begin
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        always @*
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        begin
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                $display("Sigmoid: unsupported FPWIDth.");
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                $stop;
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        end
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end
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end
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endgenerate
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initial begin
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`include "D:\Cores6\nvio\v1\rtl\fpUnit\SigTbl.ver"
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end
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// Quickly multiply number by 64 (it is in range -8 to 8) then convert to integer to get
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// table index = add 6 to exponent then convert to integer
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wire sa;
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wire [EMSB:0] xa;
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wire [FMSB:0] ma;
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fpDecomp #(FPWID) u1 (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(), .xz(), .vz(), .xinf(), .inf(), .nan() );
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reg [9:0] lutadr;
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wire [5:0] lzcnt;
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wire [MSB:0] a1;
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wire [MSB:0] i1, i2;
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wire [EMSB:0] xa1 = xa + 4'd6;
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assign a1 = {sa,xa1,ma};        // we know the exponent won't overflow
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wire [31:0] man32a = SigmoidLUT[lutadr];
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wire [31:0] man32b = lutadr==10'h3ff ? man32a : SigmoidLUT[lutadr+1];
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wire [31:0] man32;
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wire [79:0] sig80;
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generate begin : la
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if (FPWID >= 40) begin
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wire [15:0] eps = ma[FMSB-10:FMSB-10-15];
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wire [47:0] p = (man32b - man32a) * eps;
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assign man32 = man32a + (p >> 26);
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cntlz32 u3 (man32,lzcnt);
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end
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else if (FPWID==32) begin
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wire [12:0] eps = ma[FMSB-10:0];
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wire [43:0] p = (man32b - man32a) * eps;
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assign man32 = man32a + (p >> 26);
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cntlz32 u3 (man32,lzcnt);
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end
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end
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endgenerate
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wire [31:0] man32s = man32 << (lzcnt + 2'd1);    // +1 to hide leading one
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// Convert to integer
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f2i #(FPWID) u2
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(
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  .clk(clk),
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  .ce(1'b1),
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  .i(a1),
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  .o(i2)
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);
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assign i1 = i2 + 512;
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always @(posedge clk)
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  if (ce) cmp2_o <= cmp1_o;
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// We know the integer is in range 0 to 1023
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always @(posedge clk)
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  if(ce) lutadr <= i1[9:0];
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reg sa1,sa2;
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always @(posedge clk)
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if (ce) sa1 <= a[FPWID-1];
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always @(posedge clk)
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if (ce) sa2 <= sa1;
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generate begin : ooo
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if (FPWID==80) begin
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wire [14:0] ex1 = 15'h3ffe - lzcnt;
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always @(posedge clk)
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if (ce) begin
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        if (cmp2_o[1])  // abs(a) less than 8 ?
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          o <= {1'b0,ex1,man32s[31:0],32'd0};
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        else
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          o <= sa1 ? 80'h0 : `ONE80;
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end
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end
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else if (FPWID==64) begin
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wire [10:0] ex1 = 11'h3fe - lzcnt;
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always @(posedge clk)
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if (ce) begin
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        if (cmp2_o[1])  // abs(a) less than 8 ?
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          o <= {1'b0,ex1,man32s[31:0],20'd0};
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        else
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          o <= sa1 ? 64'h0 : `ONE64;
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end
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end
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else if (FPWID==40) begin
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wire [9:0] ex1 = 10'h1fe - lzcnt;
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always @(posedge clk)
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if (ce) begin
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        if (cmp2_o[1])  // abs(a) less than 8 ?
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          o <= {1'b0,ex1,man32s[31:3]};
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        else
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          o <= sa1 ? 40'h0 : `ONE40;
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end
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end
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else if (FPWID==32) begin
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wire [7:0] ex1 = 8'h7e - lzcnt;
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always @(posedge clk)
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if (ce) begin
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        if (cmp2_o[1])  // abs(a) less than 8 ?
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          o <= {1'b0,ex1,man32s[31:9]};
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        else
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          o <= sa1 ? 32'h0 : `ONE32;
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end
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end
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end
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endgenerate
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endmodule

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