OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpTrunc.sv] - Blame information for rev 76

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      fpTrunc.v
9
//              - convert floating point to integer (chop off fractional bits)
10
//              - single cycle latency floating point unit
11
//              - parameterized FPWIDth
12
//              - IEEE 754 representation
13
//
14
//
15
// This source file is free software: you can redistribute it and/or modify
16
// it under the terms of the GNU Lesser General Public License as published
17
// by the Free Software Foundation, either version 3 of the License, or
18
// (at your option) any later version.
19
//
20
// This source file is distributed in the hope that it will be useful,
21
// but WITHOUT ANY WARRANTY; without even the implied warranty of
22
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
// GNU General Public License for more details.
24
//
25
// You should have received a copy of the GNU General Public License
26
// along with this program.  If not, see .
27
//
28
// ============================================================================
29
 
30
`include "fpConfig.sv"
31
 
32
module fpTrunc(clk, ce, i, o, overflow);
33
parameter FPWID = 32;
34
`include "fpSize.sv"
35
input clk;
36
input ce;
37
input [MSB:0] i;
38
output reg [MSB:0] o;
39
output overflow;
40
 
41
 
42
integer n;
43
wire [MSB:0] maxInt  = {MSB{1'b1}};             // maximum unsigned integer value
44
wire [EMSB:0] zeroXp = {EMSB{1'b1}};    // simple constant - value of exp for zero
45
 
46
// Decompose fp value
47
reg sgn;                                                                        // sign
48
reg [EMSB:0] exp;
49
reg [FMSB:0] man;
50
reg [FMSB:0] mask;
51
 
52
wire [7:0] shamt = FMSB - (exp - zeroXp);
53
always @*
54
for (n = 0; n <= FMSB; n = n +1)
55
        mask[n] = (n > shamt);
56
 
57
always @*
58
        sgn = i[MSB];
59
always @*
60
        exp = i[MSB-1:FMSB+1];
61
always @*
62
        if (exp > zeroXp + FMSB)
63
                man = i[FMSB:0];
64
        else
65
                man = i[FMSB:0] & mask;
66
 
67
always @(posedge clk)
68
        if (ce) begin
69
                if (exp < zeroXp)
70
                        o <= 1'd0;
71
                else
72
                        o <= {sgn,exp,man};
73
        end
74
 
75
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.