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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpdivr16.v] - Blame information for rev 84

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpdivr16.v
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//    Radix 16 floating point divider primitive
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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module fpdivr16(clk, ld, a, b, q, r, done, lzcnt);
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parameter WID1 = 112;
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localparam REM = WID1 % 4;
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localparam WID = ((WID1*4)+3)/4;
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localparam DMSB = WID-1;
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input clk;
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input ld;
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input [WID-1:0] a;
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input [WID-1:0] b;
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output reg [WID*2-1:0] q = 1'd0;
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output reg [WID-1:0] r = 1'd0;
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output reg done = 1'd0;
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output reg [7:0] lzcnt = 1'd0;
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initial begin
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        if (WID % 4) begin
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                $display("fpdvir16: Width must be a multiple of four.");
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                $finish;
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        end
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end
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wire [7:0] maxcnt;
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reg [DMSB:0] rxx = 1'd0;
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reg [8:0] cnt = 1'd0;                            // iteration count
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// Simulation didn't like all the wiring.
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reg [DMSB+1:0] ri = 1'd0;
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reg b0 = 1'd0,b1 = 1'd0,b2 = 1'd0,b3 = 1'd0;
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reg [DMSB+1:0] r1 = 1'd0,r2 = 1'd0,r3 = 1'd0,r4 = 1'd0;
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reg gotnz = 0;
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assign maxcnt = WID*2/4-1;
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always @*
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        b0 = b <= {rxx,q[WID*2-1]};
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always @*
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        r1 = b0 ? {rxx,q[WID*2-1]} - b : {rxx,q[WID*2-1]};
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always @*
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        b1 = b <= {r1,q[WID*2-2]};
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always @*
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        r2 = b1 ? {r1,q[WID*2-2]} - b : {r1,q[WID*2-2]};
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always @*
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        b2 = b <= {r2,q[WID*2-3]};
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always @*
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        r3 = b2 ? {r2,q[WID*2-3]} - b : {r2,q[WID*2-3]};
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always @*
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        b3 = b <= {r3,q[WID*2-4]};
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always @*
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        r4 = b3 ? {r3,q[WID*2-4]} - b : {r3,q[WID*2-4]};
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reg [2:0] state = 0;
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always @(posedge clk)
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begin
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  if (ld) state <= 3'd1;
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  case(state)
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  3'd0: ;
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  3'd1: if (cnt[8]) state <= 3'd2;
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  3'd2: state <= 3'd0;
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  default:  state <= 3'd0;
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  endcase
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end
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always @(posedge clk)
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begin
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done <= 1'b0;
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case(state)
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3'd0:   ;
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3'd1:
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        if (!cnt[8]) begin
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                q[WID*2-1:4] <= q[WID*2-5:0];
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                q[3] <= b0;
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                q[2] <= b1;
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                q[1] <= b2;
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                q[0] <= b3;
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                if (!gotnz)
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                        casez({b0,b1,b2,b3})
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                        4'b1???:        ;
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                        4'b01??:        lzcnt <= lzcnt + 8'd1;
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                        4'b001?:        lzcnt <= lzcnt + 8'd2;
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                        4'b0001:        lzcnt <= lzcnt + 8'd3;
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                        4'b0000:        lzcnt <= lzcnt + 8'd4;
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                        endcase
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                if ({b0,b1,b2,b3} != 4'h0 && !gotnz) begin
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                        gotnz <= 3'd1;
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                end
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        rxx <= r4;
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                cnt <= cnt - 3'd1;
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        end
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3'd2:
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        begin
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        r <= r4;
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        done <= 1'b1;
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    end
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default:        ;
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endcase
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if (ld) begin
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        lzcnt <= 0;
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        gotnz <= 1'b0;
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        cnt <= {1'b0,maxcnt};
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        q <= {(a << REM),{WID{1'b0}}};
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      rxx <= {WID{1'b0}};
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end
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end
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endmodule
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