OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [i2df128.sv] - Blame information for rev 84

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 60 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2022  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      i2df128.sv
9
//  - convert integer to decimal floating point
10
//
11
// BSD 3-Clause License
12
// Redistribution and use in source and binary forms, with or without
13
// modification, are permitted provided that the following conditions are met:
14
//
15
// 1. Redistributions of source code must retain the above copyright notice, this
16
//    list of conditions and the following disclaimer.
17
//
18
// 2. Redistributions in binary form must reproduce the above copyright notice,
19
//    this list of conditions and the following disclaimer in the documentation
20
//    and/or other materials provided with the distribution.
21
//
22
// 3. Neither the name of the copyright holder nor the names of its
23
//    contributors may be used to endorse or promote products derived from
24
//    this software without specific prior written permission.
25
//
26
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
30
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
//
37
// ============================================================================
38
 
39
import DFPPkg::*;
40
 
41
module i2df128 (rst, clk, ce, ld, op, rm, i, o, done);
42
parameter FPWID=128;
43
input rst;
44
input clk;
45
input ce;
46
input ld;
47
input op;                                               // 1 = signed, 0 = unsigned
48
input [2:0] rm;                 // rounding mode
49
input [127:0] i;                // integer input
50
output [127:0] o;               // float output
51
output done;
52
 
53
wire [127:0] i1 = (op & i[127]) ? -i : i;
54
wire [171:0] bcd;
55
wire done1, done2;
56
assign done = done1 & done2;
57
 
58
DDBinToBCD ub2b1
59
(
60
        .rst(rst),
61
        .clk(clk),
62
        .ld(ld),
63
        .bin(i1),
64
        .bcd(bcd),
65
        .done(done1)
66
);
67
 
68
DFP128U ui;
69 64 robfinch
wire [13:0] zeroXp = 14'h17FF;
70 60 robfinch
 
71
reg iz;                 // zero input ?
72
wire [7:0] lz;          // count the leading zeros in the number
73
reg [7:0] lz4;          // leading zero rounded to multiple of four
74
wire [13:0] wd; // compute number of whole digits
75
reg so;                 // copy the sign of the input (easy)
76
reg [2:0] rmd;
77
wire [171:0] bcd1;
78
reg [135:0] simag;
79
 
80
always_ff @(posedge clk)
81
        rmd <= rm;
82
always_ff @(posedge clk)
83
        iz <= i==0;
84
always_ff @(posedge clk)
85
        so <= i[127];
86
 
87
delay1 #(172) u2 (.clk(clk), .ce(ce), .i(bcd),  .o(bcd1) );
88
cntlz192Reg   u4 (.clk(clk), .ce(ce), .i({bcd,20'd0}), .o(lz) );
89
 
90
always_comb
91
        lz4 = lz >> 2'd2;
92
 
93
assign wd = zeroXp - 8'd1 + 8'd34 - lz4 + 8'd9; // constant except for lz
94
 
95
reg [13:0] xo;
96
 
97
always_ff @(posedge clk)
98
        xo <= iz ? 'd0 : wd;
99
 
100
// left align number
101
// The number may to too large to represent entirely precisely in which case a
102
// right shift is required. There are only about 114 bits of precision, but the
103
// incoming number is allowed to be 128-bit.
104
// Rounding is required only when the number needs to be right-shifted.
105
 
106
always_ff @(posedge clk)
107
        if (lz4 < 8'd9)
108
                simag = bcd1 >> {8'd9 - lz4,2'd0};
109
        else
110
                simag = bcd1 << {lz4 - 8'd9,2'd0};
111
 
112
wire g =  bcd1[{8'd9 - lz4,2'd0}];      // guard bit (lsb)
113
wire r =        bcd1[{8'd9 - lz4,2'd0}-1];      // rounding bit
114
wire s = |(bcd1 & (172'd1 << {8'd9 - lz4,2'd0}-2) - 2'd1);       // "sticky" bit
115
reg rnd;
116
 
117
// Compute the round bit
118
always_ff @(posedge clk)
119
if (lz4 < 8'd9)
120
        case (rmd)
121
        3'd0:   rnd = (g & r) | (r & s);      // round to nearest even
122
        3'd1:   rnd = 0;                                        // round to zero (truncate)
123
        3'd2:   rnd = (r | s) & !so;         // round towards +infinity
124
        3'd3:   rnd = (r | s) & so;                 // round towards -infinity
125
        3'd4:   rnd = (r | s);
126
        default:        rnd = (g & r) | (r & s);      // round to nearest even
127
        endcase
128
else
129
        rnd = 1'b0;
130
 
131
// round the result
132
assign ui.sig = simag[135:0] + rnd;
133
assign ui.exp = xo[13:0];
134
assign ui.sign = op & so;
135
assign ui.nan = 1'b0;
136
assign ui.qnan = 1'b0;
137
assign ui.snan = 1'b0;
138
assign ui.infinity = 1'b0;
139
 
140
DFPPack128 upk1 (ui, o);
141
 
142
ft_delay #(.WID(1), .DEP(4)) udly1 (.clk(clk), .ce(1'b1), .i(done1), .o(done2));
143
 
144
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.