OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [i2f.v] - Blame information for rev 29

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@finitron.ca
6
//       ||
7
//
8
//      i2f.v
9
//  - convert integer to floating point
10
//  - parameterized FPWIDth
11
//  - IEEE 754 representation
12
//  - pipelineable
13
//  - single cycle latency
14
//
15
// This source file is free software: you can redistribute it and/or modify 
16
// it under the terms of the GNU Lesser General Public License as published 
17
// by the Free Software Foundation, either version 3 of the License, or     
18
// (at your option) any later version.                                      
19
//                                                                          
20
// This source file is distributed in the hope that it will be useful,      
21
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
22
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
23
// GNU General Public License for more details.                             
24
//                                                                          
25
// You should have received a copy of the GNU General Public License        
26
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
27
//                                                                          
28
// ============================================================================
29
 
30
module i2f
31
#(      parameter FPWID = 32)
32
(
33
        input clk,
34
        input ce,
35
        input [2:0] rm,                  // rounding mode
36
        input [FPWID-1:0] i,             // integer input
37
        output [FPWID-1:0] o             // float output
38
);
39
`include "fpSize.sv"
40
 
41
wire [EMSB:0] zeroXp = {EMSB{1'b1}};
42
 
43
wire iz;                        // zero input ?
44
wire [MSB:0] imag;       // get magnitude of i
45
wire [MSB:0] imag1 = i[MSB] ? -i : i;
46
wire [7:0] lz;           // count the leading zeros in the number
47
wire [EMSB:0] wd;        // compute number of whole digits
48
wire so;                        // copy the sign of the input (easy)
49
wire [2:0] rmd;
50
 
51
delay1 #(3)   u0 (.clk(clk), .ce(ce), .i(rm),     .o(rmd) );
52
delay1 #(1)   u1 (.clk(clk), .ce(ce), .i(i==0),   .o(iz) );
53
delay1 #(FPWID) u2 (.clk(clk), .ce(ce), .i(imag1),  .o(imag) );
54
delay1 #(1)   u3 (.clk(clk), .ce(ce), .i(i[MSB]), .o(so) );
55
generate
56
if (FPWID==128) begin
57
cntlz128Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
58
end else if (FPWID==96) begin
59
cntlz96Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
60
assign lz[7]=1'b0;
61
end else if (FPWID==84) begin
62
cntlz96Reg    u4 (.clk(clk), .ce(ce), .i({imag1,12'hfff}), .o(lz[6:0]) );
63
assign lz[7]=1'b0;
64
end else if (FPWID==80) begin
65
cntlz80Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
66
assign lz[7]=1'b0;
67
end else if (FPWID==64) begin
68
cntlz64Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
69
assign lz[7]=1'b0;
70
end else begin
71
cntlz32Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[5:0]) );
72
assign lz[7:6]=2'b00;
73
end
74
endgenerate
75
 
76
assign wd = zeroXp - 1 + FPWID - lz;    // constant except for lz
77
 
78
wire [EMSB:0] xo = iz ? 0 : wd;
79
wire [MSB:0] simag = imag << lz;         // left align number
80
 
81
wire g =  simag[EMSB+2];        // guard bit (lsb)
82
wire r =  simag[EMSB+1];        // rounding bit
83
wire s = |simag[EMSB:0]; // "sticky" bit
84
reg rnd;
85
 
86
// Compute the round bit
87
always @(rmd,g,r,s,so)
88
        case (rmd)
89
        3'd0:   rnd = (g & r) | (r & s);        // round to nearest even
90
        3'd1:   rnd = 0;                                 // round to zero (truncate)
91
        3'd2:   rnd = (r | s) & !so;            // round towards +infinity
92
        3'd3:   rnd = (r | s) & so;                     // round towards -infinity
93
        3'd4:   rnd = (r | s);
94
        endcase
95
 
96
// "hide" the leading one bit = MSB-1
97
// round the result
98
wire [FMSB:0] mo = simag[MSB-1:EMSB+1]+rnd;
99
 
100
assign o = {so,xo,mo};
101
 
102
endmodule
103
 
104
 
105
module i2f_tb();
106
 
107
reg clk;
108
reg [7:0] cnt;
109
wire [31:0] fo;
110
reg [31:0] i;
111
wire [79:0] fo80;
112
initial begin
113
clk = 1'b0;
114
cnt = 0;
115
end
116
always #10 clk=!clk;
117
 
118
always @(posedge clk)
119
        cnt = cnt + 1;
120
 
121
always @(cnt)
122
case(cnt)
123
8'd0:   i <= 32'd0;
124
8'd1:   i <= 32'd16777226;
125
endcase
126
 
127
i2f #(32) u1 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
128
i2f #(80) u2 (.clk(clk), .ce(1), .rm(2'd0), .i({{48{i[31]}},i}), .o(fo80) );
129
 
130
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.