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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [i2f.v] - Blame information for rev 45

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1 29 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      i2f.v
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//  - convert integer to floating point
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//  - parameterized FPWIDth
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//  - IEEE 754 representation
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//  - pipelineable
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//  - single cycle latency
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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module i2f
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#(      parameter FPWID = 32)
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(
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        input clk,
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        input ce,
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        input [2:0] rm,                  // rounding mode
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        input [FPWID-1:0] i,             // integer input
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        output [FPWID-1:0] o             // float output
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);
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`include "fpSize.sv"
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wire [EMSB:0] zeroXp = {EMSB{1'b1}};
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wire iz;                        // zero input ?
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wire [MSB:0] imag;       // get magnitude of i
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wire [MSB:0] imag1 = i[MSB] ? -i : i;
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wire [7:0] lz;           // count the leading zeros in the number
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wire [EMSB:0] wd;        // compute number of whole digits
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wire so;                        // copy the sign of the input (easy)
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wire [2:0] rmd;
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delay1 #(3)   u0 (.clk(clk), .ce(ce), .i(rm),     .o(rmd) );
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delay1 #(1)   u1 (.clk(clk), .ce(ce), .i(i==0),   .o(iz) );
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delay1 #(FPWID) u2 (.clk(clk), .ce(ce), .i(imag1),  .o(imag) );
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delay1 #(1)   u3 (.clk(clk), .ce(ce), .i(i[MSB]), .o(so) );
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generate
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if (FPWID==128) begin
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cntlz128Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz) );
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end else if (FPWID==96) begin
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cntlz96Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else if (FPWID==84) begin
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cntlz96Reg    u4 (.clk(clk), .ce(ce), .i({imag1,12'hfff}), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else if (FPWID==80) begin
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cntlz80Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else if (FPWID==64) begin
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cntlz64Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[6:0]) );
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assign lz[7]=1'b0;
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end else begin
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cntlz32Reg    u4 (.clk(clk), .ce(ce), .i(imag1), .o(lz[5:0]) );
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assign lz[7:6]=2'b00;
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end
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endgenerate
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assign wd = zeroXp - 1 + FPWID - lz;    // constant except for lz
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wire [EMSB:0] xo = iz ? 0 : wd;
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wire [MSB:0] simag = imag << lz;         // left align number
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wire g =  simag[EMSB+2];        // guard bit (lsb)
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wire r =  simag[EMSB+1];        // rounding bit
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wire s = |simag[EMSB:0]; // "sticky" bit
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reg rnd;
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// Compute the round bit
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always @(rmd,g,r,s,so)
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        case (rmd)
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        3'd0:   rnd = (g & r) | (r & s);        // round to nearest even
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        3'd1:   rnd = 0;                                 // round to zero (truncate)
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        3'd2:   rnd = (r | s) & !so;            // round towards +infinity
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        3'd3:   rnd = (r | s) & so;                     // round towards -infinity
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        3'd4:   rnd = (r | s);
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        endcase
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// "hide" the leading one bit = MSB-1
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// round the result
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wire [FMSB:0] mo = simag[MSB-1:EMSB+1]+rnd;
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assign o = {so,xo,mo};
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endmodule
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module i2f_tb();
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reg clk;
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reg [7:0] cnt;
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wire [31:0] fo;
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reg [31:0] i;
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wire [79:0] fo80;
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initial begin
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clk = 1'b0;
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cnt = 0;
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end
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always #10 clk=!clk;
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always @(posedge clk)
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        cnt = cnt + 1;
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always @(cnt)
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case(cnt)
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8'd0:   i <= 32'd0;
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8'd1:   i <= 32'd16777226;
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endcase
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i2f #(32) u1 (.clk(clk), .ce(1), .rm(2'd0), .i(i), .o(fo) );
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i2f #(80) u2 (.clk(clk), .ce(1), .rm(2'd0), .i({{48{i[31]}},i}), .o(fo80) );
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endmodule

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