OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [mult128x128seq.sv] - Blame information for rev 74

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 73 robfinch 
module mult128x128seq(clk, ld, a, b, o);
2 
input clk;
3 
input ld;
4 
input [127:0] a;
5 
input [127:0] b;
6 
output reg [255:0] o;
7 
 
8 
reg [127:0] aa = 'd0, bb ='d0;
9 
reg [256:0] acc = 'd0;
10 
wire [255:0] p1 = acc + bb;
11 
reg [11:0] count = 'd0;
12 
 
13 
always_ff @(posedge clk)
14 
begin
15 
        if (ld) begin
16 
                aa <= a;
17 
                bb <= b;
18 
                acc <= 'd0;
19 
                count <= 12'd128;
20 
        end
21 
        else begin
22 
                if (count) begin
23 
                        count <= count - 2'd1;
24 
                        if (aa[127])
25 
                                acc <= {p1,1'b0};
26 
                        else
27 
                                acc <= {acc,1'b0};
28 
                        aa <= {aa[126:0],1'b0};
29 
                end
30 
                else begin
31 
                        o <= acc[256:1];
32 
                end
33 
        end
34 
end
35 
 
36 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.