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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [mult128x128seq.sv] - Blame information for rev 90

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1 73 robfinch 
module mult128x128seq(clk, ld, a, b, o);
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input clk;
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input ld;
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input [127:0] a;
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input [127:0] b;
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output reg [255:0] o;
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reg [127:0] aa = 'd0, bb ='d0;
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reg [256:0] acc = 'd0;
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wire [255:0] p1 = acc + bb;
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reg [11:0] count = 'd0;
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always_ff @(posedge clk)
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begin
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        if (ld) begin
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                aa <= a;
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                bb <= b;
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                acc <= 'd0;
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                count <= 12'd128;
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        end
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        else begin
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                if (count) begin
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                        count <= count - 2'd1;
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                        if (aa[127])
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                                acc <= {p1,1'b0};
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                        else
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                                acc <= {acc,1'b0};
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                        aa <= {aa[126:0],1'b0};
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                end
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                else begin
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                        o <= acc[256:1];
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                end
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        end
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end
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endmodule

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