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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [positCntlz.sv] - Blame information for rev 48

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1 48 robfinch
`include "positConfig.sv"
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      positCntlz.sv
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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//
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module positCntlz(i, o);
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parameter PSTWID = `PSTWID;
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input [PSTWID-2:0] i;
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output [$clog2(PSTWID-2):0] o;
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generate begin : gClz
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  case(PSTWID)
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  16: cntlz16 u1 (.i({i,1'b1}), .o(o));
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  20: cntlz24 u1 (.i({i,1'b1,4'hF}), .o(o));
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  32: cntlz32 u1 (.i({i,1'b1}), .o(o));
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  40: cntlz48 u1 (.i({i,1'b1,8'hFF}), .o(o));
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  52: cntlz64 u1 (.i({i,1'b1,12'hFFF}), .o(o));
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  64: cntlz64 u1 (.i({i,1'b1}), .o(o));
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  80: cntlz80 u1 (.i({i,1'b1}), .o(o));
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  default:  ;
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  endcase
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end
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endgenerate
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endmodule

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