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[/] [ft816float/] [trunk/] [test_bench/] [DDBCDToBin_tb.sv] - Blame information for rev 80

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1 59 robfinch
module DDBCDToBin_tb();
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reg rst;
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reg clk;
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reg [15:0] adr;
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reg [171:0] bcd;
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reg [7:0] count;
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wire [127:0] bin;
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integer outfile;
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initial begin
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        rst = 1'b0;
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        clk = 1'b0;
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        adr = 0;
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        bcd = $urandom(1);
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        #20 rst = 1;
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        #50 rst = 0;
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        #10000000  $fclose(outfile);
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        #10 $finish;
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end
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always #5
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        clk = ~clk;
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genvar g;
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generate begin : gRand
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        for (g = 0; g < 172; g = g + 4) begin
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                always @(posedge clk) begin
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                        if (count==2)
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                                bcd[g+3:g] <= $urandom() % 10;
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                end
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        end
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end
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endgenerate
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always @(posedge clk)
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if (rst) begin
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        adr <= 0;
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        count <= 0;
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end
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else
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begin
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  if (adr==0) begin
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    outfile = $fopen("d:/cores2022/rf6809/rtl/dfpu/test_bench/DDBinToBCD_tvo.txt", "wb");
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    $fwrite(outfile, " ------ bin ------  ------ bcd ------  \n");
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  end
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        count <= count + 1;
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        if (count > 140)
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                count <= 1'd1;
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        if (adr==2) begin
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                bcd <= 172'h010;
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        end
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        if (adr==3) begin
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                bcd <= 172'h0100;
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        end
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        if (adr==4) begin
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                bcd <= 172'h12345678;
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        end
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        if (count==140) begin
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        $fwrite(outfile, "%h\t%h\n", bin, bcd);
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                adr <= adr + 1;
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        end
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end
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//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
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DDBCDToBin #(128) u6 (
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        .rst(rst),
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  .clk(clk),
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  .ld(count==3),
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  .bcd(bcd),
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  .bin(bin)
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);
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endmodule

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