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`timescale 1ns / 1ps

// ============================================================================

//        __

//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@finitron.ca

//       ||

//

//      DFPAddsub_tb.v

//              - decimal floating point addsub test bench

//

// BSD 3-Clause License

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// modification, are permitted provided that the following conditions are met:

//

// 1. Redistributions of source code must retain the above copyright notice, this

//    list of conditions and the following disclaimer.

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// 2. Redistributions in binary form must reproduce the above copyright notice,

//    this list of conditions and the following disclaimer in the documentation

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//    this software without specific prior written permission.

//

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//                                                                          

// ============================================================================

module DFPAddsub_tb();

reg rst;

reg clk;

reg [15:0] adr;

reg [127:0] a,b;

wire [127:0] o;

reg [127:0] ad,bd;

reg [127:0] od;

reg [3:0] rm;

integer n;

reg [127:0] a1, b1;

wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};

wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};

integer outfile;

initial begin

        rst = 1'b0;

        clk = 1'b0;

        adr = 0;

        a = $urandom(1);

        b = 1;

        #20 rst = 1;

        #50 rst = 0;

        #10000000  $fclose(outfile);

        #10 $finish;

end

always #5

        clk = ~clk;

genvar g;

generate begin : gRand

        for (g = 0; g < 128; g = g + 4) begin

                always @(posedge clk) begin

                        a1[g+3:g] <= $urandom() % 10;

                        b1[g+3:g] <= $urandom() % 10;

                end

        end

end

endgenerate

reg [7:0] count;

always @(posedge clk)

if (rst) begin

        adr <= 0;

        count <= 0;

end

else

begin

  if (adr==0) begin

    outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPAddsub_tvo.txt", "wb");

    $fwrite(outfile, " rm ------- A ------  ------- B ------  ------ sum -----  -- SIM Sum --\n");

  end

        count <= count + 1;

        if (count > 32)

                count <= 1'd1;

        if (count==2) begin

                a[127:0] <= a1;

                b[127:0] <= b1;

                a[127:124] <= 4'h5;

                b[127:124] <= 4'h5;

                rm <= adr[14:12];

                //ad <= memd[adr][63: 0];

                //bd <= memd[adr][127:64];

        end

        if (adr==1 && count==2) begin

                a <= 127'h50000700000000000000000000000000;

                b <= 127'h50000200000000000000000000000000;

        end

        if (adr==2 && count==2) begin

                a <= 127'h50000900000000000000000000000000;

                b <= 127'h50000200000000000000000000000000;

        end

        if (adr==3 && count==2) begin

                a <= 127'h50000000000000000000000000000000;

                b <= 127'h50000000000000000000000000000000;

        end

        if (count==31) begin

                if (adr[11]) begin

                $fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);

          end

          else begin

                $fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "+",rm, a, b, o);

          end

                adr <= adr + 1;

        end

end

//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);

DFPAddsubnr u6 (

  .clk(clk),

  .ce(1'b1),

  .op(adr[11]),

  .a(a),

  .b(b),

  .o(o),

  .rm(rm)

  );

endmodule