OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [test_bench/] [DFPAddsub_tb.v] - Blame information for rev 55

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 50 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8
//
9
//      DFPAddsub_tb.v
10
//              - decimal floating point addsub test bench
11
//
12
// BSD 3-Clause License
13
// Redistribution and use in source and binary forms, with or without
14
// modification, are permitted provided that the following conditions are met:
15
//
16
// 1. Redistributions of source code must retain the above copyright notice, this
17
//    list of conditions and the following disclaimer.
18
//
19
// 2. Redistributions in binary form must reproduce the above copyright notice,
20
//    this list of conditions and the following disclaimer in the documentation
21
//    and/or other materials provided with the distribution.
22
//
23
// 3. Neither the name of the copyright holder nor the names of its
24
//    contributors may be used to endorse or promote products derived from
25
//    this software without specific prior written permission.
26
//
27
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37
//                                                                          
38
// ============================================================================
39
 
40
module DFPAddsub_tb();
41
reg rst;
42
reg clk;
43
reg [15:0] adr;
44 55 robfinch
reg [151:0] a,b;
45
wire [151:0] o;
46
reg [151:0] ad,bd;
47
reg [151:0] od;
48 50 robfinch
reg [3:0] rm;
49
 
50
integer n;
51 55 robfinch
reg [151:0] a1, b1;
52 50 robfinch
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
53
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
54
 
55
integer outfile;
56
 
57
initial begin
58
        rst = 1'b0;
59
        clk = 1'b0;
60
        adr = 0;
61
        a = $urandom(1);
62
        b = 1;
63
        #20 rst = 1;
64
        #50 rst = 0;
65
        #10000000  $fclose(outfile);
66
        #10 $finish;
67
end
68
 
69
always #5
70
        clk = ~clk;
71
 
72
genvar g;
73
generate begin : gRand
74 55 robfinch
        for (g = 0; g < 152; g = g + 4) begin
75 50 robfinch
                always @(posedge clk) begin
76
                        a1[g+3:g] <= $urandom() % 10;
77
                        b1[g+3:g] <= $urandom() % 10;
78
                end
79
        end
80
end
81
endgenerate
82
 
83
reg [7:0] count;
84
always @(posedge clk)
85
if (rst) begin
86
        adr <= 0;
87
        count <= 0;
88
end
89
else
90
begin
91
  if (adr==0) begin
92
    outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPAddsub_tvo.txt", "wb");
93
    $fwrite(outfile, " rm ------- A ------  ------- B ------  ------ sum -----  -- SIM Sum --\n");
94
  end
95
        count <= count + 1;
96
        if (count > 32)
97
                count <= 1'd1;
98
        if (count==2) begin
99 55 robfinch
                a <= a1;
100
                b <= b1;
101
                a[151:148] <= 4'h5;
102
                b[151:148] <= 4'h5;
103 50 robfinch
                rm <= adr[14:12];
104
                //ad <= memd[adr][63: 0];
105
                //bd <= memd[adr][127:64];
106
        end
107
        if (adr==1 && count==2) begin
108 55 robfinch
                a <= 152'h50000700000000000000000000000000000000;
109
                b <= 152'h50000200000000000000000000000000000000;
110 50 robfinch
        end
111
        if (adr==2 && count==2) begin
112 55 robfinch
                a <= 152'h50000900000000000000000000000000000000;
113
                b <= 152'h50000200000000000000000000000000000000;
114 50 robfinch
        end
115
        if (adr==3 && count==2) begin
116 55 robfinch
                a <= 152'h50000000000000000000000000000000000000;
117
                b <= 152'h50000000000000000000000000000000000000;
118 50 robfinch
        end
119
        if (count==31) begin
120
                if (adr[11]) begin
121
                $fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);
122
          end
123
          else begin
124
                $fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "+",rm, a, b, o);
125
          end
126
                adr <= adr + 1;
127
        end
128
end
129
 
130
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
131
DFPAddsubnr u6 (
132
  .clk(clk),
133
  .ce(1'b1),
134
  .op(adr[11]),
135
  .a(a),
136
  .b(b),
137
  .o(o),
138
  .rm(rm)
139
  );
140
 
141
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.