OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [test_bench/] [DFPDivide_tb.v] - Blame information for rev 55

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 54 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8
//
9
//      DFPDivider_tb.v
10
//              - decimal floating point divider test bench
11
//
12
// BSD 3-Clause License
13
// Redistribution and use in source and binary forms, with or without
14
// modification, are permitted provided that the following conditions are met:
15
//
16
// 1. Redistributions of source code must retain the above copyright notice, this
17
//    list of conditions and the following disclaimer.
18
//
19
// 2. Redistributions in binary form must reproduce the above copyright notice,
20
//    this list of conditions and the following disclaimer in the documentation
21
//    and/or other materials provided with the distribution.
22
//
23
// 3. Neither the name of the copyright holder nor the names of its
24
//    contributors may be used to endorse or promote products derived from
25
//    this software without specific prior written permission.
26
//
27
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37
//
38
//                                                                          
39
//      Floating Point Multiplier / Divider
40
//
41
//      This multiplier/divider handles denormalized numbers.
42
//      The output format is of an internal expanded representation
43
//      in preparation to be fed into a normalization unit, then
44
//      rounding. Basically, it's the same as the regular format
45
//      except the mantissa is doubled in size, the leading two
46
//      bits of which are assumed to be whole bits.
47
//
48
//
49
// ============================================================================
50
 
51
module DFPDivide_tb();
52 55 robfinch
parameter N=33;
53 54 robfinch
reg rst;
54
reg clk;
55
reg [15:0] adr;
56 55 robfinch
reg [N*4+16+4-1:0] a,b;
57
wire [N*4+16+4-1:0] o;
58
reg [N*4+16+4-1:0] ad,bd;
59
wire [N*4+16+4-1:0] od;
60 54 robfinch
reg [3:0] rm;
61
wire done;
62
 
63
integer n;
64 55 robfinch
reg [N*4+16+4-1:0] a1, b1;
65 54 robfinch
reg [39:0] sum_cc;
66
 
67
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
68
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
69
 
70
integer outfile;
71
 
72
initial begin
73
        rst = 1'b0;
74
        clk = 1'b0;
75
        adr = 0;
76
        a = $urandom(1);
77
        b = 1;
78
        #20 rst = 1;
79
        #50 rst = 0;
80
        #5000000  $fclose(outfile);
81
        #10 $finish;
82
end
83
 
84
always #5
85
        clk = ~clk;
86
 
87
genvar g;
88
generate begin : gRand
89 55 robfinch
        for (g = 0; g < N*4+16+4; g = g + 4) begin
90 54 robfinch
                always @(posedge clk) begin
91
                        a1[g+3:g] <= $urandom() % 10;
92
                        b1[g+3:g] <= $urandom() % 10;
93
                end
94
        end
95
end
96
endgenerate
97
 
98
reg [9:0] count;
99
always @(posedge clk)
100
if (rst) begin
101
        adr <= 0;
102
        count <= 0;
103
        sum_cc = 0;
104
end
105
else
106
begin
107
  if (adr==0) begin
108
    outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPDivide_tvo.txt", "wb");
109
    $fwrite(outfile, "rm ------ A ------  ------- B ------  - DUT Quotient - - SIM Quotient -\n");
110
    sum_cc = 0;
111
  end
112
        count <= count + 1;
113 55 robfinch
        if (count > 750)
114 54 robfinch
                count <= 1'd1;
115
        if (count==2) begin
116 55 robfinch
                a[N*4+16+4-1:0] <= a1;
117
                b[N*4+16+4-1:0] <= b1;
118
                a[N*4+16+4-1:N*4+16+4-4] <= 4'h5;
119
                b[N*4+16+4-1:N*4+16+4-4] <= 4'h5;
120 54 robfinch
                rm <= adr[15:13];
121
                //ad <= memd[adr][63: 0];
122
                //bd <= memd[adr][127:64];
123
        end
124
        if (adr==1 && count==2) begin
125 55 robfinch
                a <= 152'h50000700000000000000000000000000000000;
126
                b <= 152'h50000200000000000000000000000000000000;
127 54 robfinch
        end
128
        if (adr==1 && count==2) begin
129 55 robfinch
                a <= 152'h50000100000000000000000000000000000000;
130
                b <= 152'h50000300000000000000000000000000000000;
131 54 robfinch
        end
132
        if (adr==2 && count==2) begin
133 55 robfinch
                a <= 152'h50000900000000000000000000000000000000;
134
                b <= 152'h50000200000000000000000000000000000000;
135 54 robfinch
        end
136
        if (adr==3 && count==2) begin
137 55 robfinch
                a <= 152'h50000000000000000000000000000000000000;
138
                b <= 152'h50000000000000000000000000000000000000;
139 54 robfinch
        end
140
        if (adr==4 && count==2) begin
141 55 robfinch
                a <= 152'h50001100000000000000000000000000000000;
142
                b <= 152'h50001100000000000000000000000000000000;
143 54 robfinch
        end
144
        if (adr==4 && count==2) begin
145 55 robfinch
                a <= 152'h50000100000000000000000000000000000000;
146
                b <= 152'h50000300000000000000000000000000000000;
147 54 robfinch
        end
148 55 robfinch
        if (count > 750) begin
149 54 robfinch
                sum_cc = sum_cc + u6.u1.u2.clkcnt;
150
          $fwrite(outfile, "%h\t%h\t%h\t%h\t%d\t%f\n", rm, a, b, o, u6.u1.u2.clkcnt, $itor(sum_cc) / $itor(adr));
151
                adr <= adr + 1;
152
        end
153
end
154
 
155
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
156 55 robfinch
DFPDividenr #(.N(N)) u6 (
157 54 robfinch
  .rst(rst),
158
  .clk(clk),
159
  .ce(1'b1),
160
  .ld(count==3),
161
  .op(1'b0),
162
  .a(a),
163
  .b(b),
164
  .o(o),
165
  .rm(rm),
166
  .done(done),
167
  .sign_exe(),
168
  .inf(),
169
  .overflow(),
170
  .underflow()
171
  );
172
 
173
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.