OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [test_bench/] [DFPScaleb96_tb.v] - Blame information for rev 83

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 78 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2006-2022  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8
//
9
//      DFPScaleb96_tb.v
10
//              - decimal floating point addsub test bench
11
//
12
// BSD 3-Clause License
13
// Redistribution and use in source and binary forms, with or without
14
// modification, are permitted provided that the following conditions are met:
15
//
16
// 1. Redistributions of source code must retain the above copyright notice, this
17
//    list of conditions and the following disclaimer.
18
//
19
// 2. Redistributions in binary form must reproduce the above copyright notice,
20
//    this list of conditions and the following disclaimer in the documentation
21
//    and/or other materials provided with the distribution.
22
//
23
// 3. Neither the name of the copyright holder nor the names of its
24
//    contributors may be used to endorse or promote products derived from
25
//    this software without specific prior written permission.
26
//
27
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37
//                                                                          
38
// ============================================================================
39
 
40
module DFPScaleb96_tb();
41
reg rst;
42
reg clk;
43
reg [15:0] adr;
44
reg [95:0] a;
45
reg [31:0] b;
46
wire [95:0] o;
47
reg [95:0] ad,bd;
48
reg [95:0] od;
49
reg [3:0] rm;
50
 
51
integer n;
52
reg [95:0] a1;
53
reg [31:0] b1;
54
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
55
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
56
 
57
integer outfile;
58
 
59
initial begin
60
        rst = 1'b0;
61
        clk = 1'b0;
62
        adr = 0;
63
        a = $urandom(1);
64
        b = 1;
65
        #20 rst = 1;
66
        #50 rst = 0;
67
        #10000000  $fclose(outfile);
68
        #10 $finish;
69
end
70
 
71
always #5
72
        clk = ~clk;
73
 
74
genvar g;
75
generate begin : gRand
76
        for (g = 0; g < 96; g = g + 4) begin
77
                always @(posedge clk) begin
78
                        a1[g+3:g] <= $urandom() % 10;
79
                end
80
        end
81
        always @(posedge clk)
82
                b1 <= $urandom();
83
end
84
endgenerate
85
 
86
reg [7:0] count;
87
always @(posedge clk)
88
if (rst) begin
89
        adr <= 0;
90
        count <= 0;
91
end
92
else
93
begin
94
  if (adr==0) begin
95
    outfile = $fopen("f:/cores2022/Float/dfpu/test_bench/DFPScaleb96_tvo.txt", "wb");
96
    $fwrite(outfile, " rm ------- A ------  ------- B ------  ------ sum -----  -- SIM Sum --\n");
97
  end
98
        count <= count + 1;
99
        if (count > 35)
100
                count <= 1'd1;
101
        if (count==2) begin
102
                a <= a1;
103
                b <= b1;
104
                a[95:92] <= 4'h5;
105
                rm <= adr[14:12];
106
                //ad <= memd[adr][63: 0];
107
                //bd <= memd[adr][127:64];
108
        end
109
 
110
//-0    543771554911558566002677        581816070341546924523033        543771554911558566002677
111
 
112
        if (adr==3 && count==2) begin
113
                a <= 96'h543771554911558566002677;
114
                b <= 32'h0;
115
                //a <= 96'h25ff00000000000000000000;    // 1
116
                //b <= 96'h25ff00000000000000000000;    // 1
117
        end
118
        if (adr==2 && count==2) begin
119
                a <= 96'h260000000000000000000000;      // 10
120
                b <= 32'h1;     // 10
121
        end
122
        if (adr==1 && count==2) begin
123
                a <= 96'h260100000000000000000000;      // 100
124
                b <= 32'h2;     // 100
125
        end
126
        if (adr==4 && count==2) begin
127
                a <= 96'h260200000000000000000000;      // 1000
128
                b <= 32'h3;     // 1000
129
        end
130
        if (adr==5 && count==2) begin
131
                a <= 96'h26064D2E7030000000000000;      // 12345678
132
                b <= 32'h1;     // 10
133
        end
134
        if (adr==6 && count==2) begin
135
                a <= 96'h440000000000000000000000;
136
                b <= 32'h4;
137
        end
138
        if (adr==7 && count==2) begin
139
                a <= 96'h440040000000000000000000;
140
                b <= 32'h5;
141
        end
142
        if (count==35) begin
143
                if (adr[11]) begin
144
                $fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);
145
          end
146
          else begin
147
                $fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "+",rm, a, b, o);
148
          end
149
                adr <= adr + 1;
150
        end
151
end
152
 
153
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
154
DFPScaleb96 u6 (
155
  .clk(clk),
156
  .ce(1'b1),
157
  .a(a),
158
  .b(b),
159
  .o(o)
160
  );
161
 
162
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.