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[/] [ft816float/] [trunk/] [test_bench/] [fpAddsub_tb.v] - Blame information for rev 47

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpAddsub_tb.v
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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module fpAddsub_tb();
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reg rst;
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reg clk;
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reg [15:0] adr;
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reg [103:0] mem [0:38000];
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reg [103:0] memo [0:38000];
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reg [199:0] memd [0:38000];
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reg [199:0] memdo [0:38000];
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reg [391:0] memq [0:38000];
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reg [391:0] memqo [0:38000];
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reg [31:0] a,b,a6,b6;
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reg [63:0] ad, bd;
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reg [127:0] aq, bq;
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wire [127:0] oq;
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wire [31:0] a5,b5;
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wire [31:0] o;
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wire [63:0] od;
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reg [3:0] rm, op, rmq, opq, rmd, opd;
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wire [3:0] rm5;
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wire [3:0] op5;
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initial begin
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        rst = 1'b0;
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        clk = 1'b0;
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        adr = 0;
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        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvs.txt", mem);
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        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvd.txt", memd);
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        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvq.txt", memq);
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        #20 rst = 1;
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        #50 rst = 0;
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end
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always #5
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        clk = ~clk;
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reg [7:0] count;
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always @(posedge clk)
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if (rst) begin
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        adr <= 0;
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        count <= 0;
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end
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else
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begin
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        count <= count + 1;
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        if (count==49)
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                count <= 0;
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        if (count==2) begin
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                a <= mem[adr][31: 0];
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                b <= mem[adr][63:32];
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                rm <= mem[adr][99:96];
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                op <= mem[adr][103:100];
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                ad <= memq[adr][63: 0];
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                bd <= memq[adr][127:64];
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                rmd <= memq[adr][195:192];
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                opd <= memq[adr][199:196];
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                aq <= memq[adr][127: 0];
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                bq <= memq[adr][255:128];
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                rmq <= memq[adr][387:384];
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                opq <= memq[adr][391:388];
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        end
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        if (count==48) begin
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                memo[adr] <= {op,rm,o,b,a};
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                memdo[adr] <= {opd,rmd,od,bd,ad};
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                memqo[adr] <= {opq,rmq,oq,bq,aq};
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                if (adr==8192) begin
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                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvso.txt", memo);
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                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvdo.txt", memdo);
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                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvqo.txt", memqo);
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                        $finish;
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                end
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                adr <= adr + 1;
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        end
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end
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fpAddsubnr #(32) u1 (clk, 1'b1, rm[2:0], op[0], a, b, o);
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fpAddsubnr #(64) u2 (clk, 1'b1, rmd[2:0], opd[0], ad, bd, od);
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fpAddsubnr #(128) u3 (clk, 1'b1, rmq[2:0], opq[0], aq, bq, oq);
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endmodule

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