OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [test_bench/] [fpFMA_tb.sv] - Blame information for rev 83

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 58 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2019-2021  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch@finitron.ca
7
//       ||
8
//
9
//      fpFMA_tb.v
10
//              - floating point multiplier - adder test bench
11
//
12
// BSD 3-Clause License
13
// Redistribution and use in source and binary forms, with or without
14
// modification, are permitted provided that the following conditions are met:
15
//
16
// 1. Redistributions of source code must retain the above copyright notice, this
17
//    list of conditions and the following disclaimer.
18
//
19
// 2. Redistributions in binary form must reproduce the above copyright notice,
20
//    this list of conditions and the following disclaimer in the documentation
21
//    and/or other materials provided with the distribution.
22
//
23
// 3. Neither the name of the copyright holder nor the names of its
24
//    contributors may be used to endorse or promote products derived from
25
//    this software without specific prior written permission.
26
//
27
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37
//
38
// ============================================================================
39
 
40
import fp::*;
41
 
42
module fpFMA_tb();
43
reg rst;
44
reg clk;
45
reg [15:0] adr;
46
reg [131:0] mem [0:24000];
47
reg [131:0] memo [0:24000];
48
reg [259:0] memd [0:24000];
49
reg [255:0] memdo [0:24000];
50
reg [31:0] a,b,c;
51
reg [3:0] rm, rmx;
52
wire [3:0] rms;
53
wire [31:0] a5,b5,c5;
54
wire [31:0] o;
55
wire [31:0] as,bs,cs;
56
reg [63:0] ad,bd,cd;
57
wire [63:0] ad5,bd5,cd5,adx,bdx,cdx;
58
wire [63:0] od;
59
reg [7:0] cnt;
60
 
61
initial begin
62
        rst = 1'b0;
63
        clk = 1'b0;
64
        adr = 0;
65
        cnt = 0;
66
        //$readmemh("d:/cores2021/ANY1/v2/rtl/fpu/test_bench/fpFMA_tv.txt", mem);
67
        $readmemh("d:/cores2021/ANY1/v2/rtl/fpu/test_bench/fpFMA_tvd.txt", memd);
68
        #20 rst = 1;
69
        #50 rst = 0;
70
end
71
 
72
always #5
73
        clk = ~clk;
74
 
75
wire [4:0] dd = 5'd27;
76
delay5 #(32) u2 (clk, 1'b1, a, a5);
77
delay5 #(32) u3 (clk, 1'b1, b, b5);
78
delay5 #(32) u4 (clk, 1'b1, c, c5);
79
delay5 #(64) u5 (clk, 1'b1, ad, ad5);
80
delay5 #(64) u6 (clk, 1'b1, bd, bd5);
81
delay5 #(64) u7 (clk, 1'b1, cd, cd5);
82
vtdl #(64,32) u8 (clk, 1'b1, dd, ad, adx);
83
vtdl #(64,32) u9 (clk, 1'b1, dd, bd, bdx);
84
vtdl #(64,32) u10 (clk, 1'b1, dd, cd, cdx);
85
vtdl #(4,32) u11 (clk, 1'b1, dd, rm, rms);
86
vtdl #(32,32) u12 (clk, 1'b1, dd, a, as);
87
vtdl #(32,32) u13 (clk, 1'b1, dd, b, bs);
88
vtdl #(32,32) u14 (clk, 1'b1, dd, c, cs);
89
 
90
always @(posedge clk)
91
if (rst) begin
92
        adr <= 0;
93
        cnt <= 0;
94
end else
95
begin
96
        cnt <= cnt + 1;
97
        if (cnt==54)
98
                cnt <= 0;
99
        if (cnt==4)
100
        begin
101
                a <= mem[adr][31: 0];
102
                b <= mem[adr][63:32];
103
                c <= mem[adr][95:64];
104
                rm <= 3'd0;//mem[adr][131:128];
105
                ad <= memd[adr][63: 0];
106
                bd <= memd[adr][127:64];
107
                cd <= memd[adr][191:128];
108
        end
109
        if (cnt==53)
110
        begin
111
                adr <= adr + 1;
112
//              memo[adr] <= {rm,o,c,b,a};
113
//              memdo[adr] <= {od,cd17,bd17,ad17};
114
                memdo[adr] <= {od,cdx,bdx,adx};
115
                if (adr==23999) begin
116
                        //$writememh("d:/cores2021/ANY1/v2/rtl/fpu/test_bench/fpFMA_tvo.txt", memo);
117
                        $writememh("d:/cores2021/ANY1/v2/rtl/fpu/test_bench/fpFMA_tvdo.txt", memdo);
118
                        $finish;
119
                end
120
        end
121
end
122
 
123
//fpFMAnr u1 (clk, 1'b1, 1'b0, rm[2:0], c, b, a, o);//, sign_exe, inf, overflow, underflow);
124
fpFMAnr u15 (clk, 1'b1, 1'b0, rm[2:0], ad, bd, cd, od);//, inf, overflow, underflow, inexact);
125
 
126
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.