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[/] [ft816float/] [trunk/] [test_bench/] [fpFMA_tb.v] - Blame information for rev 35

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`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpFMA_tb.v
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//              - floating point multiplier - adder test bench
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      Floating Point Multiplier / Divider
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//
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//      This multiplier/divider handles denormalized numbers.
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//      The output format is of an internal expanded representation
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//      in preparation to be fed into a normalization unit, then
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//      rounding. Basically, it's the same as the regular format
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//      except the mantissa is doubled in size, the leading two
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//      bits of which are assumed to be whole bits.
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//
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//
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// ============================================================================
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module fpFMA_tb();
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reg rst;
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reg clk;
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reg [15:0] adr;
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reg [131:0] mems [0:24000];
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reg [131:0] memso [0:24000];
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reg [259:0] memd [0:24000];
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reg [259:0] memdo [0:24000];
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reg [515:0] memq [0:24000];
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reg [515:0] memqo [0:24000];
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reg [31:0] a,b,c;
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reg [3:0] rm, rmd, rmq;
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wire [31:0] o;
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reg [63:0] ad,bd,cd;
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wire [63:0] od;
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reg [127:0] aq,bq,cq;
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wire [127:0] oq;
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reg [7:0] cnt;
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initial begin
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        rst = 1'b0;
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        clk = 1'b0;
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        adr = 0;
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        cnt = 0;
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        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpFMA_tvs.txt", mems);
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        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpFMA_tvd.txt", memd);
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        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpFMA_tvq.txt", memq);
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        #20 rst = 1;
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        #50 rst = 0;
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end
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always #5
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        clk = ~clk;
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always @(posedge clk)
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if (rst) begin
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        adr <= 0;
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        cnt <= 0;
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end else
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begin
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        cnt <= cnt + 1;
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        if (cnt==54)
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                cnt <= 0;
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        if (cnt==4)
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        begin
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                a <= mems[adr][31: 0];
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                b <= mems[adr][63:32];
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                c <= mems[adr][95:64];
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                rm <= mems[adr][131:128];
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                ad <= memd[adr][63: 0];
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                bd <= memd[adr][127:64];
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                cd <= memd[adr][191:128];
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                rmd <= memd[adr][259:256];
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                aq <= memq[adr][127: 0];
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                bq <= memq[adr][255:128];
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                cq <= memq[adr][383:256];
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                rmq <= memq[adr][515:512];
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        end
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        if (cnt==53)
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        begin
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                adr <= adr + 1;
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                memso[adr] <= {rm,o,c,b,a};
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                memdo[adr] <= {rmd,od,cd,bd,ad};
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                memqo[adr] <= {rmq,oq,cq,bq,aq};
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                //memdo[adr] <= {rmd,od,cdx,bdx,adx};
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                if (adr==8191) begin
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                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpFMA_tvso.txt", memso);
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                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpFMA_tvdo.txt", memdo);
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                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpFMA_tvqo.txt", memqo);
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                        $finish;
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                end
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        end
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end
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fpFMAnr #(32) u1 (clk, 1'b1, 1'b0, rm[2:0], c, b, a, o);//, sign_exe, inf, overflow, underflow);
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fpFMAnr #(64) u16 (clk, 1'b1, 1'b0, rmd[2:0], ad, bd, cd, od);//, sign_exe, inf, overflow, underflow);
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fpFMAnr #(128) u17 (clk, 1'b1, 1'b0, rmq[2:0], cq, bq, aq, oq);//, sign_exe, inf, overflow, underflow);
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//fpFMAnr #(64) u15 (clk, 1'b1, 1'b0, rmd[2:0], ad, bd, cd, od);//, inf, overflow, underflow, inexact);
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endmodule

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