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[/] [ft816float/] [trunk/] [test_bench/] [fpRsqrte_tb.sv] - Blame information for rev 33

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1 17 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2017-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      fpRsqrte_tb.v
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//              - test reciprocal square root estimate
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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//
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// This module returns the sigmoid of a number using a lookup table.
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// -1.0 or +1.0 is returned for entries outside of the range -8.0 to +8.0
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//
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//
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// ============================================================================
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module fpRsqrte_tb();
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reg clk, rst;
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reg [12:0] ndx;
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wire [31:0] o;
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reg [5:0] cnt;
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reg [63:0] mem [0:8191];
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reg [63:0] memo [0:8191];
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reg ld;
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initial begin
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  #0 rst = 1'b0;
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  #0 clk = 1'b0;
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        $readmemh("d:/cores6/rtfItanium/v1/rtl/fpUnit/test_bench/fpRsqrte_tv.txt", mem);
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  #10 rst = 1'b1;
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  #40 rst = 1'b0;
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end
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always #5 clk = ~clk;
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wire [31:0] a = mem[ndx][31:0];
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wire [79:0] a1, o3;
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F32ToF80 u2 (a, a1);
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fpRsqrte #(80) u1 (clk, 1'b1, ld, a1, o3);
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F80ToF32 u3 (o3, o);
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always @(posedge clk)
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if (rst)
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  cnt = 0;
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else begin
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  cnt = cnt + 2'd1;
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end
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always @(posedge clk)
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if (rst)
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  ndx = 0;
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else begin
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        ld <= 1'b0;
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        if (cnt==6'd0)
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                ld <= 1'b1;
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        if (cnt==6'd63) begin
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                memo[ndx] <= {o,a};
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        ndx = ndx + 2'd1;
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  end
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        if (ndx==8191) begin
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                $writememh("d:/cores6/rtfItanium/v1/rtl/fpUnit/test_bench/fpRsqrte_tvo.txt", memo);
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                $finish;
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        end
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end
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wire [31:0] o1, o2;
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// Multiply number by 4096 (it is in range -1 to 1) then convert to integer
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assign o1[22:0] = o[22:0];
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assign o1[30:23] = o[30:23] + 8'd12; // we know this won't overflow
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assign o1[31] = o[31];
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f2i #(32) u4
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(
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  .clk(clk),
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  .ce(1'b1),
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  .i(o1),
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  .o(o2)
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);
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endmodule

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