OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [test_bench/] [fpSigmoid_tb.sv] - Blame information for rev 57

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 17 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2017-2019  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      sigmoid_tb.v
9
//              - test sigmoid
10
//
11
//
12
// This source file is free software: you can redistribute it and/or modify
13
// it under the terms of the GNU Lesser General Public License as published
14
// by the Free Software Foundation, either version 3 of the License, or
15
// (at your option) any later version.
16
//
17
// This source file is distributed in the hope that it will be useful,
18
// but WITHOUT ANY WARRANTY; without even the implied warranty of
19
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20
// GNU General Public License for more details.
21
//
22
// You should have received a copy of the GNU General Public License
23
// along with this program.  If not, see .
24
//
25
//
26
// This module returns the sigmoid of a number using a lookup table.
27
// -1.0 or +1.0 is returned for entries outside of the range -8.0 to +8.0
28
//
29
//
30
// ============================================================================
31
 
32
module sigmoid_tb();
33
reg clk, rst;
34
reg [12:0] ndx;
35
wire [31:0] o;
36
 
37
initial begin
38
  #0 rst = 1'b0;
39
  #0 clk = 1'b0;
40
  #10 rst = 1'b1;
41
  #40 rst = 1'b0;
42
end
43
 
44
always #5 clk = ~clk;
45
 
46
reg [31:0] RngLUT [0:8191];
47
initial begin
48
`include "D:\Cores6\rtfItanium\v1\rtl\fpUnit\RangeTbl.ver"
49
end
50
 
51
fpSigmoid #(32) u1 (clk, 1'b1, RngLUT[ndx], o);
52
 
53
always @(posedge clk)
54
if (rst)
55
  ndx = 0;
56
else begin
57
  ndx = ndx + 13'd1;
58
end
59
 
60
wire [31:0] o1, o2;
61
// Multiply number by 4096 (it is in range -1 to 1) then convert to integer
62
assign o1[22:0] = o[22:0];
63
assign o1[30:23] = o[30:23] + 8'd12; // we know this won't overflow
64
assign o1[31] = o[31];
65
 
66
f2i #(32) u2
67
(
68
  .clk(clk),
69
  .ce(1'b1),
70
  .i(o1),
71
  .o(o2)
72
);
73
 
74
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.