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[/] [ft816float/] [trunk/] [test_bench/] [fpSqrt_tb.v] - Blame information for rev 33

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Line No. Rev Author Line
1 28 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpSqrt_tb.v
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//              - floating point square root test bench
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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module fpSqrt_tb();
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reg rst;
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reg clk;
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reg clk4x;
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reg [12:0] adr;
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reg [63:0] mem [0:8191];
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reg [63:0] memo [0:9000];
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reg [127:0] memd [0:8191];
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reg [127:0] memdo [0:9000];
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reg [159:0] memdx [0:8191];
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reg [159:0] memdxo [0:8191];
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reg [31:0] a,a6;
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reg [63:0] ad;
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wire [31:0] a5;
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wire [31:0] o;
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wire [63:0] od;
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reg [79:0] adx;
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wire [79:0] odx;
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reg ld;
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wire done;
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reg [3:0] state;
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reg [7:0] count;
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initial begin
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        rst = 1'b0;
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        clk = 1'b0;
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        clk4x = 0;
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        adr = 0;
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        $readmemh("d:/cores6/cs01/rtl/fp/test_bench/fpSqrt_tv.txt", mem);
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        $readmemh("d:/cores6/cs01/rtl/fp/test_bench/fpSqrt_tvd.txt", memd);
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        $readmemh("d:/cores6/cs01/rtl/fp/test_bench/fpSqrt_tvdx.txt", memdx);
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        #20 rst = 1;
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        #50 rst = 0;
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end
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always #8
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        clk = ~clk;
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always @(posedge clk)
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if (rst) begin
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        adr = 0;
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        state <= 1;
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        count <= 0;
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end
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else
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begin
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        ld <= 1'b0;
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case(state)
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4'd1:
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        begin
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                count <= 8'd0;
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                a <= mem[adr][31: 0];
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                ad <= memd[adr][63:0];
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                adx <= memdx[adr][79:0];
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                ld <= 1'b1;
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                state <= 2;
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        end
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4'd2:
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        begin
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                count <= count + 2'd1;
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                if (count==8'd160) begin
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                        memo[adr] <= {o,a};
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                        memdo[adr] <= {od,ad};
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                        memdxo[adr] <= {odx,adx};
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                        adr <= adr + 1;
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                        if (adr==8191) begin
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                                $writememh("d:/cores6/cs01/rtl/fp/test_bench/fpSqrt_tvo.txt", memo);
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                                $writememh("d:/cores6/cs01/rtl/fp/test_bench/fpSqrt_tvdo.txt", memdo);
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                                $writememh("d:/cores6/cs01/rtl/fp/test_bench/fpSqrt_tvdxo.txt", memdxo);
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                                $finish;
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                        end
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                        state <= 3;
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                end
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        end
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4'd3:   state <= 4;
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4'd4:   state <= 5;
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4'd5:   state <= 1;
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endcase
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end
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fpSqrtnr #(32) u1 (rst, clk, 1'b1, ld, a, o, 3'b000);//, sign_exe, inf, overflow, underflow);
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fpSqrtnr #(64) u2 (rst, clk, 1'b1, ld, ad, od, 3'b000, done);//, sign_exe, inf, overflow, underflow);
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fpSqrtnr #(80) u3 (rst, clk, 1'b1, ld, adx, odx, 3'b000, done);//, sign_exe, inf, overflow, underflow);
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endmodule

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