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[/] [fully-pipelined-edge-detection-algorithms/] [trunk/] [src/] [ScharrFilter.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 13 muhammedko
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: MUHAMMED KOCAOGLU
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-- 
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-- Create Date: 01/13/2022 10:56:24 PM
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-- Design Name: 
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-- Module Name: ScharrFilter - Behavioral
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-- Project Name: 
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-- Target Devices: 
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-- Tool Versions: 
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-- Description: 
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-- 
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-- Dependencies: 
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-- 
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- 
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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USE work.OperatorOverloading_pkg.ALL;
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USE work.EdgeDetection_pkg.ALL;
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ENTITY ScharrFilter IS
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    PORT (
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        CLK                     : IN STD_LOGIC;
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        EdgeDetection_Enable    : IN STD_LOGIC;
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        EdgeDetection_Disable   : IN STD_LOGIC;
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        EdgeDetection_Din       : IN array2D(0 TO 2)(7 DOWNTO 0);
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        EdgeDetection_Dout      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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        EdgeDetection_Ready     : OUT STD_LOGIC
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    );
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END ScharrFilter;
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ARCHITECTURE Behavioral OF ScharrFilter IS
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signal Din_Buffer               : array3D(0 to 2)(0 to 2)(7 downto 0)   := (others => (others => (others => '0')));
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signal MultArray_Reg_x          : array3D(0 to 2)(0 to 2)(16 downto 0)  := (others => (others => (others => '0')));
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signal AddArray_Layer1_x        : array2D(0 to 2)(16 downto 0)          := (others => (others => '0'));
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signal AddArray_Layer2_x        : std_logic_vector(16 downto 0)         := (others => '0');
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signal Convolution_Res_x        : std_logic_vector(33 downto 0)         := (others => '0');
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signal MultArray_Reg_y          : array3D(0 to 2)(0 to 2)(16 downto 0)  := (others => (others => (others => '0')));
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signal AddArray_Layer1_y        : array2D(0 to 2)(16 downto 0)          := (others => (others => '0'));
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signal AddArray_Layer2_y        : std_logic_vector(16 downto 0)         := (others => '0');
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signal Convolution_Res_y        : std_logic_vector(33 downto 0)         := (others => '0');
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signal EdgeDetection_Dout_Reg   : STD_LOGIC_VECTOR(33 DOWNTO 0)         := (others => '0');
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    TYPE states IS (
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        S_IDLE,
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        S_CONVOLVE
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    );
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    SIGNAL state : states := S_IDLE;
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    constant Coeff_x : array3D(0 to 2)(0 to 2)(7 downto 0) := (
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        (x"03", x"00", x"fd"),
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        (x"0A", x"00", x"f6"),
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        (x"03", x"00", x"fd")
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    );
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    constant Coeff_y : array3D(0 to 2)(0 to 2)(7 downto 0) := (
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        (x"03", x"0A", x"03"),
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        (x"00", x"00", x"00"),
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        (x"fd", x"f6", x"fd")
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    );
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    signal cntr         : integer range 0 to 7 := 0;
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    signal cntrDisable  : integer range 0 to 7 := 0;
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BEGIN
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    P_MAIN : PROCESS (CLK)
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    BEGIN
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        IF rising_edge(CLK) THEN
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            CASE state IS
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                WHEN S_IDLE =>
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                    EdgeDetection_Ready <= '0';
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                    IF EdgeDetection_Enable THEN
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                        state <= S_CONVOLVE;
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                        Din_Buffer(0)           <=  EdgeDetection_Din;
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                        Din_Buffer(1 to 2)      <= Din_Buffer(0 to 1);
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                        cntr                    <= 0;
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                    END IF;
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                WHEN S_CONVOLVE =>
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                    Din_Buffer(0)               <=  EdgeDetection_Din;
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                    Din_Buffer(1 to 2)          <= Din_Buffer(0 to 1);
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                    MultArray_Reg_x             <= Coeff_x * ("0" & Din_Buffer);
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                    AddArray_Layer1_x(0)        <= std_logic_vector(signed(MultArray_Reg_x(0)(0)) + signed(MultArray_Reg_x(0)(1))  + signed(MultArray_Reg_x(0)(2)));
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                    AddArray_Layer1_x(1)        <= std_logic_vector(signed(MultArray_Reg_x(1)(0)) + signed(MultArray_Reg_x(1)(1))  + signed(MultArray_Reg_x(1)(2)));
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                    AddArray_Layer1_x(2)        <= std_logic_vector(signed(MultArray_Reg_x(2)(0)) + signed(MultArray_Reg_x(2)(1))  + signed(MultArray_Reg_x(2)(2)));
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                    AddArray_Layer2_x           <= std_logic_vector(signed(AddArray_Layer1_x(0)) + signed(AddArray_Layer1_x(1)) + signed(AddArray_Layer1_x(2)));
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                    Convolution_Res_x           <= std_logic_vector(signed(AddArray_Layer2_x) * signed(AddArray_Layer2_x));
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                    MultArray_Reg_y             <= Coeff_y * ("0" & Din_Buffer);
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                    AddArray_Layer1_y(0)        <= std_logic_vector(signed(MultArray_Reg_y(0)(0)) + signed(MultArray_Reg_y(0)(1))  + signed(MultArray_Reg_y(0)(2)));
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                    AddArray_Layer1_y(1)        <= std_logic_vector(signed(MultArray_Reg_y(1)(0)) + signed(MultArray_Reg_y(1)(1))  + signed(MultArray_Reg_y(1)(2)));
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                    AddArray_Layer1_y(2)        <= std_logic_vector(signed(MultArray_Reg_y(2)(0)) + signed(MultArray_Reg_y(2)(1))  + signed(MultArray_Reg_y(2)(2)));
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                    AddArray_Layer2_y           <= std_logic_vector(signed(AddArray_Layer1_y(0)) + signed(AddArray_Layer1_y(1)) + signed(AddArray_Layer1_y(2)));
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                    Convolution_Res_y           <= std_logic_vector(signed(AddArray_Layer2_y) * signed(AddArray_Layer2_y));
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                    EdgeDetection_Dout_Reg  <= std_logic_vector(unsigned(Convolution_Res_x) + unsigned(Convolution_Res_y));
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                    if cntr = 5 then
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                        cntr    <= 0;
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                        EdgeDetection_Ready <= '1';
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                    else
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                        cntr    <= cntr + 1;
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                    end if;
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                    if EdgeDetection_Disable = '1' then
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                        cntrDisable <= cntrDisable + 1;
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                    end if;
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                    if cntrDisable = 6 then
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                        state   <= S_IDLE;
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                        EdgeDetection_Ready <= '0';
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                        cntr    <= 0;
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                        cntrDisable <= 0;
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                    end if;
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            END CASE;
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        END IF;
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    END PROCESS;
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    EdgeDetection_Dout  <= EdgeDetection_Dout_Reg(31 downto 0);
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END Behavioral;

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