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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [1.0/] [nios_ii_sdram.1.0.xml] - Blame information for rev 188

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        Altera
        ip.hwp.cpu
        nios_ii_sdram
        1.0
        Nios2 SDRAM subsystem.
        
                
                        clk
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                clk_0
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        hibi_master
                        
                        
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_av_out_from_the_hibi_pe_dma_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                hibi_comm_out_from_the_hibi_pe_dma_1
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                hibi_data_out_from_the_hibi_pe_dma_1
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                RE
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_re_out_from_the_hibi_pe_dma_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                WE
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_we_out_from_the_hibi_pe_dma_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        rst_n
                        
                        
                        
                        false
                        
                                
                                        
                                                RESETn
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                reset_n
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        sdram_if
                        
                        
                        
                        false
                        
                                
                                        
                                                sdram_address_out
                                                
                                                        11
                                                        0
                                                
                                        
                                        
                                                zs_addr_from_the_sdram_1
                                                
                                                        11
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_ba_out
                                                
                                                        1
                                                        0
                                                
                                        
                                        
                                                zs_ba_from_the_sdram_1
                                                
                                                        1
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_cas_n_out
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                zs_cas_n_from_the_sdram_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_cke_out
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                zs_cke_from_the_sdram_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_cs_n_out
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                zs_cs_n_from_the_sdram_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_ras_n_out
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                zs_ras_n_from_the_sdram_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_data_inout
                                                
                                                        15
                                                        0
                                                
                                        
                                        
                                                zs_dq_to_and_from_the_sdram_1
                                                
                                                        15
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_we_n_out
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                zs_we_n_from_the_sdram_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                sdram_dqm_out
                                                
                                                        1
                                                        0
                                                
                                        
                                        
                                                zs_dqm_from_the_sdram_1
                                                
                                                        1
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        hibi_slave
                        
                        
                        
                                
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_av_in_to_the_hibi_pe_dma_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                hibi_comm_in_to_the_hibi_pe_dma_1
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                hibi_data_in_to_the_hibi_pe_dma_1
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                EMPTY
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_empty_in_to_the_hibi_pe_dma_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                hibi_full_in_to_the_hibi_pe_dma_1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        avalon_addr_space
                        Avalon address space. (local)
                        4G
                        32
                        
                                
                                        .bss
                                        0x00800000
                                        512
                                
                                
                                        .exceptions
                                        0x00800200
                                        512
                                
                                
                                        .entry
                                        0x00800400
                                        512
                                
                                
                                        .stack
                                        0x00800600
                                        512
                                
                                
                                        .heap
                                        0x00800800
                                        512
                                
                                
                                        .rwdata
                                        0x00800A00
                                        512
                                
                                
                                        .text
                                        0x00800C00
                                        512
                                
                                
                                        .rodata
                                        0x00800E00
                                        512
                                
                                
                                        Shared_memory
                                        0x1000000
                                        4K
                                
                        
                        8
                        
                                avalon_addr_space
                                
                                        HIBI_PE_DMA
                                        0x0
                                        4
                                        32
                                        reserved
                                        
                                                RX_INITIALIZE
                                                Initializes the channel
                                                0
                                                0x0
                                                32
                                                false
                                                write-only
                                        
                                        
                                                CONTROL
                                                Control register
                                                0
                                                0x1
                                                32
                                                false
                                                read-write
                                        
                                        
                                                IRQ_STATUS
                                                Read IRQ status and acknoledge interrupts
                                                0
                                                0x2
                                                32
                                                false
                                                read-write
                                        
                                        
                                                TX_MEM_ADDR
                                                Address where data to be sent begins
                                                0
                                                0x3
                                                32
                                                false
                                                write-only
                                        
                                        
                                                TX_WORDS
                                                How many words to send
                                                0
                                                0x4
                                                32
                                                false
                                                read-only
                                        
                                        
                                                TX_COMM
                                                Hibi command to send the data with
                                                0
                                                0x5
                                                32
                                                false
                                                write-only
                                        
                                        
                                                TX_HIBI_ADDR
                                                Hibi address to send the data
                                                0
                                                0x6
                                                32
                                                false
                                                write-only
                                        
                                        
                                                RX_HIBI_DATA
                                                Current data on hibi rx interface
                                                0
                                                0x7
                                                32
                                                false
                                                read-only
                                        
                                        
                                                RX_MEM_ADDR
                                                Address where channel n stores received data
                                                0
                                                0x8
                                                32
                                                false
                                                read-write
                                        
                                        
                                                RX_WORDS
                                                How many words to receive for packet channel n or read
                                                0
                                                0x9
                                                32
                                                read-write
                                        
                                        
                                                RX_HIBI_ADDR
                                                Hibi address for channel n to listen
                                                0
                                                0xA
                                                32
                                                false
                                                read-write
                                        
                                
                                
                                        JTAG_UART
                                        0x4
                                        4
                                        32
                                        reserved
                                
                                
                                        TIMER
                                        0x8
                                        4
                                        32
                                        reserved
                                
                                
                                        SYSID
                                        0x10
                                        4
                                        32
                                        reserved
                                
                                
                                        ONCHIP_MEM
                                        0x1000000
                                        4K
                                        32
                                        memory
                                
                                
                                        SDRAM
                                        0x00800000
                                        8M
                                        32
                                        memory
                                
                        
                
                
                        hibi_addr_space
                        HIBI address space
                        4G
                        32
                        8
                
        
        
                
                        hibi_mem_map
                        
                                hibi_addr_block
                                0x0
                                32
                                32
                                reserved
                        
                        32
                
        
        
                
                        
                                rtl
                                ::
                                
                                        hdlSources
                                
                        
                
                
                        
                                clk_0
                                
                                        in
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                hibi_av_in_to_the_hibi_pe_dma_1
                                
                                        in
                                
                                
                        
                        
                                hibi_av_out_from_the_hibi_pe_dma_1
                                
                                        out
                                
                                
                        
                        
                                hibi_comm_in_to_the_hibi_pe_dma_1
                                
                                        in
                                        
                                                4
                                                0
                                        
                                
                                
                        
                        
                                hibi_comm_out_from_the_hibi_pe_dma_1
                                
                                        out
                                        
                                                4
                                                0
                                        
                                
                                
                        
                        
                                hibi_data_in_to_the_hibi_pe_dma_1
                                
                                        in
                                        
                                                31
                                                0
                                        
                                
                                
                        
                        
                                hibi_data_out_from_the_hibi_pe_dma_1
                                
                                        out
                                        
                                                31
                                                0
                                        
                                
                                
                        
                        
                                hibi_empty_in_to_the_hibi_pe_dma_1
                                
                                        in
                                
                                
                        
                        
                                hibi_full_in_to_the_hibi_pe_dma_1
                                
                                        in
                                
                                
                        
                        
                                hibi_re_out_from_the_hibi_pe_dma_1
                                
                                        out
                                
                                
                        
                        
                                hibi_we_out_from_the_hibi_pe_dma_1
                                
                                        out
                                
                                
                        
                        
                                reset_n
                                
                                        in
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                zs_addr_from_the_sdram_1
                                
                                        out
                                        
                                                11
                                                0
                                        
                                
                                
                        
                        
                                zs_ba_from_the_sdram_1
                                
                                        out
                                        
                                                1
                                                0
                                        
                                
                                
                        
                        
                                zs_cas_n_from_the_sdram_1
                                
                                        out
                                
                                
                        
                        
                                zs_cke_from_the_sdram_1
                                
                                        out
                                
                                
                        
                        
                                zs_cs_n_from_the_sdram_1
                                
                                        out
                                
                                
                        
                        
                                zs_dq_to_and_from_the_sdram_1
                                
                                        inout
                                        
                                                15
                                                0
                                        
                                
                                
                        
                        
                                zs_dqm_from_the_sdram_1
                                
                                        out
                                        
                                                1
                                                0
                                        
                                
                                
                        
                        
                                zs_ras_n_from_the_sdram_1
                                
                                        out
                                
                                
                        
                        
                                zs_we_n_from_the_sdram_1
                                
                                        out
                                
                                
                        
                
        
        
                
                        hdlSources
                        
                                ../hdl/cpu_1.v
                                verilogSource
                                false
                        
                        
                                ../hdl/cpu_1_jtag_debug_module_sysclk.v
                                verilogSource
                                false
                        
                        
                                ../hdl/cpu_1_jtag_debug_module_tck.v
                                verilogSource
                                false
                        
                        
                                ../hdl/cpu_1_jtag_debug_module_wrapper.v
                                verilogSource
                                false
                        
                        
                                ../hdl/cpu_1_mult_cell.v
                                verilogSource
                                false
                        
                        
                                ../hdl/cpu_1_oci_test_bench.v
                                verilogSource
                                false
                        
                        
                                ../hdl/cpu_1_test_bench.v
                                verilogSource
                                false
                        
                        
                                ../hdl/hibi_pe_dma_1.vhd
                                vhdlSource
                                false
                        
                        
                                ../hdl/jtag_uart_1.v
                                verilogSource
                                false
                        
                        
                                ../hdl/nios_ii_sdram.qip
                                quartusIPFile
                                false
                        
                        
                                ../hdl/nios_ii_sdram.v
                                verilogSource
                                false
                        
                        
                                ../hdl/onchip_memory_1.v
                                verilogSource
                                false
                        
                        
                                ../hdl/sdram_1.v
                                verilogSource
                                false
                        
                        
                                ../hdl/timer_1.v
                                verilogSource
                                false
                        
                
        
        
                
                        nios2
                        
                
        
        
                
                        
                                IP
                                HW
                                Fixed
                        
                        
                                
                                        software
                                        
                                
                        
                
        


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Tools

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [1.0/] [nios_ii_sdram.1.0.xml] - Blame information for rev 188

Line No.	Rev	Author	Line
1	147	lanttu
2
3
4
5
6
7			`Altera`
8			`ip.hwp.cpu`
9			`nios_ii_sdram`
10			`1.0`
11	157	lanttu	`Nios2 SDRAM subsystem.`
12	147	lanttu
13
14			`clk`
15
16
17
18			`false`
19
20
21
22			`CLK`
23
24			`0`
25			`0`
26
27
28
29			`clk_0`
30
31			`0`
32			`0`
33
34
35
36
37			`8`
38			`little`
39
40
41			`hibi_master`
42
43
44
45			`false`
46
47
48
49			`AV`
50
51			`0`
52			`0`
53
54
55
56			`hibi_av_out_from_the_hibi_pe_dma_1`
57
58			`0`
59			`0`
60
61
62
63
64
65			`COMM`
66
67			`4`
68			`0`
69
70
71
72			`hibi_comm_out_from_the_hibi_pe_dma_1`
73
74			`4`
75			`0`
76
77
78
79
80
81			`DATA`
82
83			`31`
84			`0`
85
86
87
88			`hibi_data_out_from_the_hibi_pe_dma_1`
89
90			`31`
91			`0`
92
93
94
95
96
97			`RE`
98
99			`0`
100			`0`
101
102
103
104			`hibi_re_out_from_the_hibi_pe_dma_1`
105
106			`0`
107			`0`
108
109
110
111
112
113			`WE`
114
115			`0`
116			`0`
117
118
119
120			`hibi_we_out_from_the_hibi_pe_dma_1`
121
122			`0`
123			`0`
124
125
126
127
128			`8`
129			`little`
130
131
132			`rst_n`
133
134
135
136			`false`
137
138
139
140			`RESETn`
141
142			`0`
143			`0`
144
145
146
147			`reset_n`
148
149			`0`
150			`0`
151
152
153
154
155			`8`
156			`little`
157
158
159			`sdram_if`
160
161
162
163			`false`
164
165
166
167			`sdram_address_out`
168
169			`11`
170			`0`
171
172
173
174			`zs_addr_from_the_sdram_1`
175
176			`11`
177			`0`
178
179
180
181
182
183			`sdram_ba_out`
184
185			`1`
186			`0`
187
188
189
190			`zs_ba_from_the_sdram_1`
191
192			`1`
193			`0`
194
195
196
197
198
199			`sdram_cas_n_out`
200
201			`0`
202			`0`
203
204
205
206			`zs_cas_n_from_the_sdram_1`
207
208			`0`
209			`0`
210
211
212
213
214
215			`sdram_cke_out`
216
217			`0`
218			`0`
219
220
221
222			`zs_cke_from_the_sdram_1`
223
224			`0`
225			`0`
226
227
228
229
230
231			`sdram_cs_n_out`
232
233			`0`
234			`0`
235
236
237
238			`zs_cs_n_from_the_sdram_1`
239
240			`0`
241			`0`
242
243
244
245
246
247			`sdram_ras_n_out`
248
249			`0`
250			`0`
251
252
253
254			`zs_ras_n_from_the_sdram_1`
255
256			`0`
257			`0`
258
259
260
261
262
263			`sdram_data_inout`
264
265			`15`
266			`0`
267
268
269
270			`zs_dq_to_and_from_the_sdram_1`
271
272			`15`
273			`0`
274
275
276
277
278
279			`sdram_we_n_out`
280
281			`0`
282			`0`
283
284
285
286			`zs_we_n_from_the_sdram_1`
287
288			`0`
289			`0`
290
291
292
293
294
295			`sdram_dqm_out`
296
297			`1`
298			`0`
299
300
301
302			`zs_dqm_from_the_sdram_1`
303
304			`1`
305			`0`
306
307
308
309
310			`8`
311			`little`
312
313
314			`hibi_slave`
315
316
317	157	lanttu
318
319
320	147	lanttu	`false`
321
322
323
324			`AV`
325
326			`0`
327			`0`
328
329
330
331			`hibi_av_in_to_the_hibi_pe_dma_1`
332
333			`0`
334			`0`
335
336
337
338
339
340			`COMM`
341
342			`4`
343			`0`
344
345
346
347			`hibi_comm_in_to_the_hibi_pe_dma_1`
348
349			`4`
350			`0`
351
352
353
354
355
356			`DATA`
357
358			`31`
359			`0`
360
361
362
363			`hibi_data_in_to_the_hibi_pe_dma_1`
364
365			`31`
366			`0`
367
368
369
370
371
372			`EMPTY`
373
374			`0`
375			`0`
376
377
378
379			`hibi_empty_in_to_the_hibi_pe_dma_1`
380
381			`0`
382			`0`
383
384
385
386
387
388			`FULL`
389
390			`0`
391			`0`
392
393
394
395			`hibi_full_in_to_the_hibi_pe_dma_1`
396
397			`0`
398			`0`
399
400
401
402
403			`8`
404			`little`
405
406
407
408
409	157	lanttu	`avalon_addr_space`
410			`Avalon address space. (local)`
411			`4G`
412			`32`
413
414
415			`.bss`
416			`0x00800000`
417			`512`
418
419
420			`.exceptions`
421			`0x00800200`
422			`512`
423
424
425			`.entry`
426			`0x00800400`
427			`512`
428
429
430			`.stack`
431			`0x00800600`
432			`512`
433
434
435			`.heap`
436			`0x00800800`
437			`512`
438
439
440			`.rwdata`
441			`0x00800A00`
442			`512`
443
444
445			`.text`
446			`0x00800C00`
447			`512`
448
449
450			`.rodata`
451			`0x00800E00`
452			`512`
453
454
455			`Shared_memory`
456			`0x1000000`
457			`4K`
458
459
460	147	lanttu	`8`
461	157	lanttu
462			`avalon_addr_space`
463
464			`HIBI_PE_DMA`
465			`0x0`
466			`4`
467			`32`
468			`reserved`
469	188	lanttu
470			`RX_INITIALIZE`
471			`Initializes the channel`
472			`0`
473			`0x0`
474			`32`
475			`false`
476			`write-only`
477
478
479			`CONTROL`
480			`Control register`
481			`0`
482			`0x1`
483			`32`
484			`false`
485			`read-write`
486
487
488			`IRQ_STATUS`
489			`Read IRQ status and acknoledge interrupts`
490			`0`
491			`0x2`
492			`32`
493			`false`
494			`read-write`
495
496
497			`TX_MEM_ADDR`
498			`Address where data to be sent begins`
499			`0`
500			`0x3`
501			`32`
502			`false`
503			`write-only`
504
505
506			`TX_WORDS`
507			`How many words to send`
508			`0`
509			`0x4`
510			`32`
511			`false`
512			`read-only`
513
514
515			`TX_COMM`
516			`Hibi command to send the data with`
517			`0`
518			`0x5`
519			`32`
520			`false`
521			`write-only`
522
523
524			`TX_HIBI_ADDR`
525			`Hibi address to send the data`
526			`0`
527			`0x6`
528			`32`
529			`false`
530			`write-only`
531
532
533			`RX_HIBI_DATA`
534			`Current data on hibi rx interface`
535			`0`
536			`0x7`
537			`32`
538			`false`
539			`read-only`
540
541
542			`RX_MEM_ADDR`
543			`Address where channel n stores received data`
544			`0`
545			`0x8`
546			`32`
547			`false`
548			`read-write`
549
550
551			`RX_WORDS`
552			`How many words to receive for packet channel n or read`
553			`0`
554			`0x9`
555			`32`
556			`read-write`
557
558
559			`RX_HIBI_ADDR`
560			`Hibi address for channel n to listen`
561			`0`
562			`0xA`
563			`32`
564			`false`
565			`read-write`
566
567	157	lanttu
568
569			`JTAG_UART`
570			`0x4`
571			`4`
572			`32`
573			`reserved`
574
575
576			`TIMER`
577			`0x8`
578			`4`
579			`32`
580			`reserved`
581
582
583			`SYSID`
584			`0x10`
585			`4`
586			`32`
587			`reserved`
588
589
590			`ONCHIP_MEM`
591			`0x1000000`
592			`4K`
593			`32`
594			`memory`
595
596
597			`SDRAM`
598			`0x00800000`
599			`8M`
600			`32`
601			`memory`
602
603
604	147	lanttu
605	157	lanttu
606			`hibi_addr_space`
607			`HIBI address space`
608			`4G`
609			`32`
610			`8`
611
612	147	lanttu
613	157	lanttu
614
615			`hibi_mem_map`
616	188	lanttu
617			`hibi_addr_block`
618			`0x0`
619			`32`
620			`32`
621			`reserved`
622
623	157	lanttu	`32`
624
625
626	147	lanttu
627
628
629			`rtl`
630			`::`
631
632			`hdlSources`
633
634
635
636
637
638			`clk_0`
639
640			`in`
641
642			`0`
643			`0`
644
645
646
647
648
649			`hibi_av_in_to_the_hibi_pe_dma_1`
650
651			`in`
652
653
654
655
656			`hibi_av_out_from_the_hibi_pe_dma_1`
657
658			`out`
659
660
661
662
663			`hibi_comm_in_to_the_hibi_pe_dma_1`
664
665			`in`
666
667			`4`
668			`0`
669
670
671
672
673
674			`hibi_comm_out_from_the_hibi_pe_dma_1`
675
676			`out`
677
678			`4`
679			`0`
680
681
682
683
684
685			`hibi_data_in_to_the_hibi_pe_dma_1`
686
687			`in`
688
689			`31`
690			`0`
691
692
693
694
695
696			`hibi_data_out_from_the_hibi_pe_dma_1`
697
698			`out`
699
700			`31`
701			`0`
702
703
704
705
706
707			`hibi_empty_in_to_the_hibi_pe_dma_1`
708
709			`in`
710
711
712
713
714			`hibi_full_in_to_the_hibi_pe_dma_1`
715
716			`in`
717
718
719
720
721			`hibi_re_out_from_the_hibi_pe_dma_1`
722
723			`out`
724
725
726
727
728			`hibi_we_out_from_the_hibi_pe_dma_1`
729
730			`out`
731
732
733
734
735			`reset_n`
736
737			`in`
738
739			`0`
740			`0`
741
742
743
744
745
746			`zs_addr_from_the_sdram_1`
747
748			`out`
749
750			`11`
751			`0`
752
753
754
755
756
757			`zs_ba_from_the_sdram_1`
758
759			`out`
760
761			`1`
762			`0`
763
764
765
766
767
768			`zs_cas_n_from_the_sdram_1`
769
770			`out`
771
772
773
774
775			`zs_cke_from_the_sdram_1`
776
777			`out`
778
779
780
781
782			`zs_cs_n_from_the_sdram_1`
783
784			`out`
785
786
787
788
789			`zs_dq_to_and_from_the_sdram_1`
790
791			`inout`
792
793			`15`
794			`0`
795
796
797
798
799
800			`zs_dqm_from_the_sdram_1`
801
802			`out`
803
804			`1`
805			`0`
806
807
808
809
810
811			`zs_ras_n_from_the_sdram_1`
812
813			`out`
814
815
816
817
818			`zs_we_n_from_the_sdram_1`
819
820			`out`
821
822
823
824
825
826
827
828			`hdlSources`
829
830	157	lanttu	`../hdl/cpu_1.v`
831	147	lanttu	`verilogSource`
832			`false`
833
834
835	157	lanttu	`../hdl/cpu_1_jtag_debug_module_sysclk.v`
836	147	lanttu	`verilogSource`
837			`false`
838
839
840	157	lanttu	`../hdl/cpu_1_jtag_debug_module_tck.v`
841	147	lanttu	`verilogSource`
842			`false`
843
844
845	157	lanttu	`../hdl/cpu_1_jtag_debug_module_wrapper.v`
846	147	lanttu	`verilogSource`
847			`false`
848
849
850	157	lanttu	`../hdl/cpu_1_mult_cell.v`
851	147	lanttu	`verilogSource`
852			`false`
853
854
855	157	lanttu	`../hdl/cpu_1_oci_test_bench.v`
856			`verilogSource`
857	147	lanttu	`false`
858
859
860	157	lanttu	`../hdl/cpu_1_test_bench.v`
861	147	lanttu	`verilogSource`
862			`false`
863
864
865	157	lanttu	`../hdl/hibi_pe_dma_1.vhd`
866			`vhdlSource`
867	147	lanttu	`false`
868
869
870	157	lanttu	`../hdl/jtag_uart_1.v`
871	147	lanttu	`verilogSource`
872			`false`
873
874
875	157	lanttu	`../hdl/nios_ii_sdram.qip`
876			`quartusIPFile`
877	147	lanttu	`false`
878
879
880	157	lanttu	`../hdl/nios_ii_sdram.v`
881	147	lanttu	`verilogSource`
882			`false`
883
884
885	157	lanttu	`../hdl/onchip_memory_1.v`
886	147	lanttu	`verilogSource`
887			`false`
888
889
890	157	lanttu	`../hdl/sdram_1.v`
891	147	lanttu	`verilogSource`
892			`false`
893
894
895	157	lanttu	`../hdl/timer_1.v`
896	147	lanttu	`verilogSource`
897			`false`
898
899
900
901
902
903			`nios2`
904	157	lanttu
905	147	lanttu
906
907
908
909
910			`IP`
911			`HW`
912			`Fixed`
913
914
915
916			`software`
917
918
919
920
921
922