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//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module cpu_1_mult_cell (
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// inputs:
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A_mul_src1,
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A_mul_src2,
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clk,
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reset_n,
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// outputs:
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A_mul_cell_result
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)
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;
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output [ 31: 0] A_mul_cell_result;
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input [ 31: 0] A_mul_src1;
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input [ 31: 0] A_mul_src2;
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input clk;
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input reset_n;
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wire [ 31: 0] A_mul_cell_result;
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wire [ 31: 0] A_mul_cell_result_part_1;
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wire [ 15: 0] A_mul_cell_result_part_2;
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wire mul_clr;
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assign mul_clr = ~reset_n;
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altmult_add the_altmult_add_part_1
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(
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.aclr0 (mul_clr),
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.clock0 (clk),
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.dataa (A_mul_src1[15 : 0]),
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.datab (A_mul_src2[15 : 0]),
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.ena0 (1'b1),
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.result (A_mul_cell_result_part_1)
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);
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defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
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the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
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the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
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the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
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the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
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the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
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the_altmult_add_part_1.input_source_a0 = "DATAA",
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the_altmult_add_part_1.input_source_b0 = "DATAB",
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the_altmult_add_part_1.intended_device_family = "CYCLONEII",
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the_altmult_add_part_1.lpm_type = "altmult_add",
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the_altmult_add_part_1.multiplier1_direction = "ADD",
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the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
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the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
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the_altmult_add_part_1.number_of_multipliers = 1,
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the_altmult_add_part_1.output_register = "UNREGISTERED",
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the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
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the_altmult_add_part_1.port_signa = "PORT_UNUSED",
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the_altmult_add_part_1.port_signb = "PORT_UNUSED",
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the_altmult_add_part_1.representation_a = "UNSIGNED",
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the_altmult_add_part_1.representation_b = "UNSIGNED",
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the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
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the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
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the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
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the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
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the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
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the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
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the_altmult_add_part_1.width_a = 16,
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the_altmult_add_part_1.width_b = 16,
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the_altmult_add_part_1.width_result = 32;
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altmult_add the_altmult_add_part_2
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(
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.aclr0 (mul_clr),
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.clock0 (clk),
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.dataa (A_mul_src1[31 : 16]),
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.datab (A_mul_src2[15 : 0]),
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.ena0 (1'b1),
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.result (A_mul_cell_result_part_2)
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);
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defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
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the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
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the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
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the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
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the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
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the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
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the_altmult_add_part_2.input_source_a0 = "DATAA",
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the_altmult_add_part_2.input_source_b0 = "DATAB",
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the_altmult_add_part_2.intended_device_family = "CYCLONEII",
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the_altmult_add_part_2.lpm_type = "altmult_add",
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the_altmult_add_part_2.multiplier1_direction = "ADD",
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the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
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the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
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the_altmult_add_part_2.number_of_multipliers = 1,
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the_altmult_add_part_2.output_register = "UNREGISTERED",
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the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
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the_altmult_add_part_2.port_signa = "PORT_UNUSED",
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the_altmult_add_part_2.port_signb = "PORT_UNUSED",
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the_altmult_add_part_2.representation_a = "UNSIGNED",
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the_altmult_add_part_2.representation_b = "UNSIGNED",
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the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
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the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
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the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
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the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
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the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
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the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
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the_altmult_add_part_2.width_a = 16,
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the_altmult_add_part_2.width_b = 16,
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the_altmult_add_part_2.width_result = 16;
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assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
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A_mul_cell_result_part_2,
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A_mul_cell_result_part_1[15 : 0]};
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endmodule
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