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[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sram/] [1.0/] [hdl/] [cpu_0_jtag_debug_module_tck.v] - Blame information for rev 154

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1 147 lanttu 
//Legal Notice: (C)2012 Altera Corporation. All rights reserved.  Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors.  Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module cpu_0_jtag_debug_module_tck (
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                                     // inputs:
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                                      MonDReg,
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                                      break_readreg,
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                                      dbrk_hit0_latch,
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                                      dbrk_hit1_latch,
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                                      dbrk_hit2_latch,
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                                      dbrk_hit3_latch,
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                                      debugack,
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                                      ir_in,
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                                      jtag_state_rti,
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                                      monitor_error,
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                                      monitor_ready,
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                                      reset_n,
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                                      resetlatch,
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                                      tck,
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                                      tdi,
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                                      tracemem_on,
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                                      tracemem_trcdata,
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                                      tracemem_tw,
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                                      trc_im_addr,
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                                      trc_on,
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                                      trc_wrap,
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                                      trigbrktype,
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                                      trigger_state_1,
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                                      vs_cdr,
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                                      vs_sdr,
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                                      vs_uir,
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                                     // outputs:
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                                      ir_out,
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                                      jrst_n,
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                                      sr,
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                                      st_ready_test_idle,
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                                      tdo
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                                   )
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;
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  output  [  1: 0] ir_out;
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  output           jrst_n;
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  output  [ 37: 0] sr;
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  output           st_ready_test_idle;
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  output           tdo;
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  input   [ 31: 0] MonDReg;
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  input   [ 31: 0] break_readreg;
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  input            dbrk_hit0_latch;
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  input            dbrk_hit1_latch;
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  input            dbrk_hit2_latch;
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  input            dbrk_hit3_latch;
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  input            debugack;
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  input   [  1: 0] ir_in;
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  input            jtag_state_rti;
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  input            monitor_error;
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  input            monitor_ready;
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  input            reset_n;
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  input            resetlatch;
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  input            tck;
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  input            tdi;
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  input            tracemem_on;
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  input   [ 35: 0] tracemem_trcdata;
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  input            tracemem_tw;
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  input   [  6: 0] trc_im_addr;
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  input            trc_on;
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  input            trc_wrap;
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  input            trigbrktype;
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  input            trigger_state_1;
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  input            vs_cdr;
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  input            vs_sdr;
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  input            vs_uir;
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  reg     [  2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
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  wire             debugack_sync;
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  reg     [  1: 0] ir_out;
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  wire             jrst_n;
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  wire             monitor_ready_sync;
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  reg     [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
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  wire             st_ready_test_idle;
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  wire             tdo;
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  wire             unxcomplemented_resetxx0;
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  wire             unxcomplemented_resetxx1;
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  always @(posedge tck)
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    begin
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      if (vs_cdr)
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          case (ir_in)
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              2'b00: begin
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                  sr[35] <= debugack_sync;
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                  sr[34] <= monitor_error;
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                  sr[33] <= resetlatch;
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                  sr[32 : 1] <= MonDReg;
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                  sr[0] <= monitor_ready_sync;
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              end // 2'b00
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              2'b01: begin
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                  sr[35 : 0] <= tracemem_trcdata;
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                  sr[37] <= tracemem_tw;
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                  sr[36] <= tracemem_on;
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              end // 2'b01
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              2'b10: begin
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                  sr[37] <= trigger_state_1;
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                  sr[36] <= dbrk_hit3_latch;
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                  sr[35] <= dbrk_hit2_latch;
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                  sr[34] <= dbrk_hit1_latch;
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                  sr[33] <= dbrk_hit0_latch;
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                  sr[32 : 1] <= break_readreg;
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                  sr[0] <= trigbrktype;
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              end // 2'b10
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              2'b11: begin
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                  sr[15 : 12] <= 1'b0;
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                  sr[11 : 2] <= trc_im_addr;
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                  sr[1] <= trc_wrap;
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                  sr[0] <= trc_on;
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              end // 2'b11
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          endcase // ir_in
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      if (vs_sdr)
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          case (DRsize)
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              3'b000: begin
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                  sr <= {tdi, sr[37 : 2], tdi};
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              end // 3'b000
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              3'b001: begin
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                  sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
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              end // 3'b001
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              3'b010: begin
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                  sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
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              end // 3'b010
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              3'b011: begin
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                  sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
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              end // 3'b011
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              3'b100: begin
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                  sr <= {tdi, sr[37],         tdi, sr[35 : 1]};
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              end // 3'b100
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              3'b101: begin
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                  sr <= {tdi, sr[37 : 1]};
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              end // 3'b101
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              default: begin
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                  sr <= {tdi, sr[37 : 2], tdi};
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              end // default
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          endcase // DRsize
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      if (vs_uir)
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          case (ir_in)
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              2'b00: begin
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                  DRsize <= 3'b100;
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              end // 2'b00
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              2'b01: begin
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                  DRsize <= 3'b101;
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              end // 2'b01
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              2'b10: begin
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                  DRsize <= 3'b101;
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              end // 2'b10
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              2'b11: begin
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                  DRsize <= 3'b010;
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              end // 2'b11
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          endcase // ir_in
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    end
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  assign tdo = sr[0];
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  assign st_ready_test_idle = jtag_state_rti;
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  assign unxcomplemented_resetxx0 = jrst_n;
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  altera_std_synchronizer the_altera_std_synchronizer
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    (
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      .clk (tck),
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      .din (debugack),
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      .dout (debugack_sync),
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      .reset_n (unxcomplemented_resetxx0)
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    );
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  defparam the_altera_std_synchronizer.depth = 2;
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  assign unxcomplemented_resetxx1 = jrst_n;
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  altera_std_synchronizer the_altera_std_synchronizer1
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    (
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      .clk (tck),
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      .din (monitor_ready),
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      .dout (monitor_ready_sync),
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      .reset_n (unxcomplemented_resetxx1)
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    );
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  defparam the_altera_std_synchronizer1.depth = 2;
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  always @(posedge tck or negedge jrst_n)
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    begin
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      if (jrst_n == 0)
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          ir_out <= 2'b0;
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      else
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        ir_out <= {debugack_sync, monitor_ready_sync};
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    end
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//synthesis translate_off
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//////////////// SIMULATION-ONLY CONTENTS
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  assign jrst_n = reset_n;
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//////////////// END SIMULATION-ONLY CONTENTS
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//synthesis translate_on
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//synthesis read_comments_as_HDL on
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//  assign jrst_n = 1;
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//synthesis read_comments_as_HDL off
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endmodule
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