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lanttu |
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module cpu_0_test_bench (
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// inputs:
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A_bstatus_reg,
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A_cmp_result,
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A_ctrl_exception,
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A_ctrl_ld_non_bypass,
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A_dst_regnum,
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A_en,
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A_estatus_reg,
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A_ienable_reg,
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A_ipending_reg,
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A_iw,
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A_mem_byte_en,
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A_op_hbreak,
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A_op_intr,
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A_pcb,
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A_st_data,
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A_status_reg,
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A_valid,
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A_wr_data_unfiltered,
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A_wr_dst_reg,
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E_add_br_to_taken_history_unfiltered,
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E_logic_result,
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E_valid,
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M_bht_ptr_unfiltered,
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M_bht_wr_data_unfiltered,
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M_bht_wr_en_unfiltered,
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M_mem_baddr,
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M_target_pcb,
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M_valid,
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W_dst_regnum,
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W_iw,
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W_iw_op,
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W_iw_opx,
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W_pcb,
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W_valid,
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W_vinst,
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W_wr_dst_reg,
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clk,
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d_address,
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d_byteenable,
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d_read,
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d_write,
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i_address,
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i_read,
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i_readdatavalid,
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reset_n,
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// outputs:
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A_wr_data_filtered,
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E_add_br_to_taken_history_filtered,
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E_src1_eq_src2,
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M_bht_ptr_filtered,
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M_bht_wr_data_filtered,
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M_bht_wr_en_filtered,
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test_has_ended
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)
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;
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output [ 31: 0] A_wr_data_filtered;
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output E_add_br_to_taken_history_filtered;
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output E_src1_eq_src2;
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output [ 7: 0] M_bht_ptr_filtered;
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output [ 1: 0] M_bht_wr_data_filtered;
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output M_bht_wr_en_filtered;
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output test_has_ended;
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input [ 31: 0] A_bstatus_reg;
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input A_cmp_result;
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input A_ctrl_exception;
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input A_ctrl_ld_non_bypass;
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input [ 4: 0] A_dst_regnum;
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input A_en;
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input [ 31: 0] A_estatus_reg;
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input [ 31: 0] A_ienable_reg;
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input [ 31: 0] A_ipending_reg;
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input [ 31: 0] A_iw;
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input [ 3: 0] A_mem_byte_en;
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input A_op_hbreak;
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input A_op_intr;
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input [ 20: 0] A_pcb;
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input [ 31: 0] A_st_data;
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input [ 31: 0] A_status_reg;
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input A_valid;
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input [ 31: 0] A_wr_data_unfiltered;
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input A_wr_dst_reg;
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input E_add_br_to_taken_history_unfiltered;
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input [ 31: 0] E_logic_result;
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input E_valid;
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input [ 7: 0] M_bht_ptr_unfiltered;
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input [ 1: 0] M_bht_wr_data_unfiltered;
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input M_bht_wr_en_unfiltered;
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input [ 20: 0] M_mem_baddr;
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input [ 20: 0] M_target_pcb;
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input M_valid;
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input [ 4: 0] W_dst_regnum;
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input [ 31: 0] W_iw;
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input [ 5: 0] W_iw_op;
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input [ 5: 0] W_iw_opx;
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input [ 20: 0] W_pcb;
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input W_valid;
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input [ 55: 0] W_vinst;
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input W_wr_dst_reg;
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input clk;
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input [ 20: 0] d_address;
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input [ 3: 0] d_byteenable;
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input d_read;
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input d_write;
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input [ 20: 0] i_address;
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input i_read;
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input i_readdatavalid;
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input reset_n;
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reg [ 20: 0] A_mem_baddr;
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reg [ 20: 0] A_target_pcb;
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wire [ 31: 0] A_wr_data_filtered;
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wire A_wr_data_unfiltered_0_is_x;
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wire A_wr_data_unfiltered_10_is_x;
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wire A_wr_data_unfiltered_11_is_x;
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wire A_wr_data_unfiltered_12_is_x;
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wire A_wr_data_unfiltered_13_is_x;
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wire A_wr_data_unfiltered_14_is_x;
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wire A_wr_data_unfiltered_15_is_x;
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wire A_wr_data_unfiltered_16_is_x;
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wire A_wr_data_unfiltered_17_is_x;
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wire A_wr_data_unfiltered_18_is_x;
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wire A_wr_data_unfiltered_19_is_x;
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wire A_wr_data_unfiltered_1_is_x;
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wire A_wr_data_unfiltered_20_is_x;
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wire A_wr_data_unfiltered_21_is_x;
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wire A_wr_data_unfiltered_22_is_x;
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wire A_wr_data_unfiltered_23_is_x;
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wire A_wr_data_unfiltered_24_is_x;
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wire A_wr_data_unfiltered_25_is_x;
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wire A_wr_data_unfiltered_26_is_x;
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wire A_wr_data_unfiltered_27_is_x;
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wire A_wr_data_unfiltered_28_is_x;
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wire A_wr_data_unfiltered_29_is_x;
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wire A_wr_data_unfiltered_2_is_x;
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wire A_wr_data_unfiltered_30_is_x;
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wire A_wr_data_unfiltered_31_is_x;
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wire A_wr_data_unfiltered_3_is_x;
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wire A_wr_data_unfiltered_4_is_x;
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wire A_wr_data_unfiltered_5_is_x;
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wire A_wr_data_unfiltered_6_is_x;
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wire A_wr_data_unfiltered_7_is_x;
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wire A_wr_data_unfiltered_8_is_x;
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wire A_wr_data_unfiltered_9_is_x;
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wire E_add_br_to_taken_history_filtered;
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wire E_src1_eq_src2;
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wire [ 7: 0] M_bht_ptr_filtered;
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wire [ 1: 0] M_bht_wr_data_filtered;
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wire M_bht_wr_en_filtered;
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wire W_op_add;
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wire W_op_addi;
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wire W_op_and;
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wire W_op_andhi;
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wire W_op_andi;
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wire W_op_beq;
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wire W_op_bge;
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wire W_op_bgeu;
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wire W_op_blt;
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wire W_op_bltu;
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wire W_op_bne;
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wire W_op_br;
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wire W_op_break;
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wire W_op_bret;
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wire W_op_call;
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wire W_op_callr;
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wire W_op_cmpeq;
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wire W_op_cmpeqi;
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wire W_op_cmpge;
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wire W_op_cmpgei;
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wire W_op_cmpgeu;
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wire W_op_cmpgeui;
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wire W_op_cmplt;
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wire W_op_cmplti;
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wire W_op_cmpltu;
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wire W_op_cmpltui;
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wire W_op_cmpne;
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wire W_op_cmpnei;
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wire W_op_crst;
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wire W_op_custom;
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wire W_op_div;
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wire W_op_divu;
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wire W_op_eret;
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wire W_op_flushd;
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wire W_op_flushda;
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wire W_op_flushi;
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wire W_op_flushp;
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wire W_op_hbreak;
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wire W_op_initd;
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wire W_op_initda;
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wire W_op_initi;
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wire W_op_intr;
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wire W_op_jmp;
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wire W_op_jmpi;
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wire W_op_ldb;
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wire W_op_ldbio;
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wire W_op_ldbu;
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wire W_op_ldbuio;
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wire W_op_ldh;
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wire W_op_ldhio;
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wire W_op_ldhu;
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wire W_op_ldhuio;
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wire W_op_ldl;
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wire W_op_ldw;
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wire W_op_ldwio;
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wire W_op_mul;
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wire W_op_muli;
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wire W_op_mulxss;
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wire W_op_mulxsu;
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wire W_op_mulxuu;
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wire W_op_nextpc;
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wire W_op_nor;
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wire W_op_opx;
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wire W_op_or;
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wire W_op_orhi;
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wire W_op_ori;
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wire W_op_rdctl;
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wire W_op_rdprs;
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wire W_op_ret;
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wire W_op_rol;
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wire W_op_roli;
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wire W_op_ror;
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wire W_op_rsv02;
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wire W_op_rsv09;
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wire W_op_rsv10;
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wire W_op_rsv17;
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wire W_op_rsv18;
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wire W_op_rsv25;
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wire W_op_rsv26;
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wire W_op_rsv33;
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wire W_op_rsv34;
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wire W_op_rsv41;
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wire W_op_rsv42;
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wire W_op_rsv49;
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wire W_op_rsv57;
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wire W_op_rsv61;
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wire W_op_rsv62;
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wire W_op_rsv63;
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wire W_op_rsvx00;
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wire W_op_rsvx10;
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wire W_op_rsvx15;
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wire W_op_rsvx17;
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wire W_op_rsvx21;
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wire W_op_rsvx25;
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wire W_op_rsvx33;
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wire W_op_rsvx34;
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wire W_op_rsvx35;
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wire W_op_rsvx42;
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wire W_op_rsvx43;
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wire W_op_rsvx44;
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wire W_op_rsvx47;
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wire W_op_rsvx50;
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wire W_op_rsvx51;
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wire W_op_rsvx55;
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wire W_op_rsvx56;
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wire W_op_rsvx60;
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wire W_op_rsvx63;
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wire W_op_sll;
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wire W_op_slli;
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wire W_op_sra;
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wire W_op_srai;
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wire W_op_srl;
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wire W_op_srli;
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wire W_op_stb;
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wire W_op_stbio;
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wire W_op_stc;
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wire W_op_sth;
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wire W_op_sthio;
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wire W_op_stw;
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wire W_op_stwio;
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wire W_op_sub;
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294 |
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wire W_op_sync;
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295 |
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wire W_op_trap;
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wire W_op_wrctl;
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wire W_op_wrprs;
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298 |
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wire W_op_xor;
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299 |
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wire W_op_xorhi;
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300 |
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wire W_op_xori;
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301 |
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wire test_has_ended;
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302 |
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assign W_op_call = W_iw_op == 0;
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303 |
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assign W_op_jmpi = W_iw_op == 1;
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304 |
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assign W_op_ldbu = W_iw_op == 3;
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305 |
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assign W_op_addi = W_iw_op == 4;
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306 |
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assign W_op_stb = W_iw_op == 5;
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307 |
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assign W_op_br = W_iw_op == 6;
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308 |
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assign W_op_ldb = W_iw_op == 7;
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309 |
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assign W_op_cmpgei = W_iw_op == 8;
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310 |
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assign W_op_ldhu = W_iw_op == 11;
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311 |
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assign W_op_andi = W_iw_op == 12;
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312 |
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assign W_op_sth = W_iw_op == 13;
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313 |
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assign W_op_bge = W_iw_op == 14;
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314 |
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assign W_op_ldh = W_iw_op == 15;
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315 |
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assign W_op_cmplti = W_iw_op == 16;
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316 |
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assign W_op_initda = W_iw_op == 19;
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317 |
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assign W_op_ori = W_iw_op == 20;
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318 |
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assign W_op_stw = W_iw_op == 21;
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319 |
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assign W_op_blt = W_iw_op == 22;
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320 |
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assign W_op_ldw = W_iw_op == 23;
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321 |
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assign W_op_cmpnei = W_iw_op == 24;
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322 |
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assign W_op_flushda = W_iw_op == 27;
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323 |
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assign W_op_xori = W_iw_op == 28;
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324 |
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assign W_op_stc = W_iw_op == 29;
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325 |
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assign W_op_bne = W_iw_op == 30;
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326 |
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assign W_op_ldl = W_iw_op == 31;
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327 |
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assign W_op_cmpeqi = W_iw_op == 32;
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328 |
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assign W_op_ldbuio = W_iw_op == 35;
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329 |
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assign W_op_muli = W_iw_op == 36;
|
330 |
|
|
assign W_op_stbio = W_iw_op == 37;
|
331 |
|
|
assign W_op_beq = W_iw_op == 38;
|
332 |
|
|
assign W_op_ldbio = W_iw_op == 39;
|
333 |
|
|
assign W_op_cmpgeui = W_iw_op == 40;
|
334 |
|
|
assign W_op_ldhuio = W_iw_op == 43;
|
335 |
|
|
assign W_op_andhi = W_iw_op == 44;
|
336 |
|
|
assign W_op_sthio = W_iw_op == 45;
|
337 |
|
|
assign W_op_bgeu = W_iw_op == 46;
|
338 |
|
|
assign W_op_ldhio = W_iw_op == 47;
|
339 |
|
|
assign W_op_cmpltui = W_iw_op == 48;
|
340 |
|
|
assign W_op_initd = W_iw_op == 51;
|
341 |
|
|
assign W_op_orhi = W_iw_op == 52;
|
342 |
|
|
assign W_op_stwio = W_iw_op == 53;
|
343 |
|
|
assign W_op_bltu = W_iw_op == 54;
|
344 |
|
|
assign W_op_ldwio = W_iw_op == 55;
|
345 |
|
|
assign W_op_rdprs = W_iw_op == 56;
|
346 |
|
|
assign W_op_flushd = W_iw_op == 59;
|
347 |
|
|
assign W_op_xorhi = W_iw_op == 60;
|
348 |
|
|
assign W_op_rsv02 = W_iw_op == 2;
|
349 |
|
|
assign W_op_rsv09 = W_iw_op == 9;
|
350 |
|
|
assign W_op_rsv10 = W_iw_op == 10;
|
351 |
|
|
assign W_op_rsv17 = W_iw_op == 17;
|
352 |
|
|
assign W_op_rsv18 = W_iw_op == 18;
|
353 |
|
|
assign W_op_rsv25 = W_iw_op == 25;
|
354 |
|
|
assign W_op_rsv26 = W_iw_op == 26;
|
355 |
|
|
assign W_op_rsv33 = W_iw_op == 33;
|
356 |
|
|
assign W_op_rsv34 = W_iw_op == 34;
|
357 |
|
|
assign W_op_rsv41 = W_iw_op == 41;
|
358 |
|
|
assign W_op_rsv42 = W_iw_op == 42;
|
359 |
|
|
assign W_op_rsv49 = W_iw_op == 49;
|
360 |
|
|
assign W_op_rsv57 = W_iw_op == 57;
|
361 |
|
|
assign W_op_rsv61 = W_iw_op == 61;
|
362 |
|
|
assign W_op_rsv62 = W_iw_op == 62;
|
363 |
|
|
assign W_op_rsv63 = W_iw_op == 63;
|
364 |
|
|
assign W_op_eret = W_op_opx & (W_iw_opx == 1);
|
365 |
|
|
assign W_op_roli = W_op_opx & (W_iw_opx == 2);
|
366 |
|
|
assign W_op_rol = W_op_opx & (W_iw_opx == 3);
|
367 |
|
|
assign W_op_flushp = W_op_opx & (W_iw_opx == 4);
|
368 |
|
|
assign W_op_ret = W_op_opx & (W_iw_opx == 5);
|
369 |
|
|
assign W_op_nor = W_op_opx & (W_iw_opx == 6);
|
370 |
|
|
assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7);
|
371 |
|
|
assign W_op_cmpge = W_op_opx & (W_iw_opx == 8);
|
372 |
|
|
assign W_op_bret = W_op_opx & (W_iw_opx == 9);
|
373 |
|
|
assign W_op_ror = W_op_opx & (W_iw_opx == 11);
|
374 |
|
|
assign W_op_flushi = W_op_opx & (W_iw_opx == 12);
|
375 |
|
|
assign W_op_jmp = W_op_opx & (W_iw_opx == 13);
|
376 |
|
|
assign W_op_and = W_op_opx & (W_iw_opx == 14);
|
377 |
|
|
assign W_op_cmplt = W_op_opx & (W_iw_opx == 16);
|
378 |
|
|
assign W_op_slli = W_op_opx & (W_iw_opx == 18);
|
379 |
|
|
assign W_op_sll = W_op_opx & (W_iw_opx == 19);
|
380 |
|
|
assign W_op_wrprs = W_op_opx & (W_iw_opx == 20);
|
381 |
|
|
assign W_op_or = W_op_opx & (W_iw_opx == 22);
|
382 |
|
|
assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23);
|
383 |
|
|
assign W_op_cmpne = W_op_opx & (W_iw_opx == 24);
|
384 |
|
|
assign W_op_srli = W_op_opx & (W_iw_opx == 26);
|
385 |
|
|
assign W_op_srl = W_op_opx & (W_iw_opx == 27);
|
386 |
|
|
assign W_op_nextpc = W_op_opx & (W_iw_opx == 28);
|
387 |
|
|
assign W_op_callr = W_op_opx & (W_iw_opx == 29);
|
388 |
|
|
assign W_op_xor = W_op_opx & (W_iw_opx == 30);
|
389 |
|
|
assign W_op_mulxss = W_op_opx & (W_iw_opx == 31);
|
390 |
|
|
assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32);
|
391 |
|
|
assign W_op_divu = W_op_opx & (W_iw_opx == 36);
|
392 |
|
|
assign W_op_div = W_op_opx & (W_iw_opx == 37);
|
393 |
|
|
assign W_op_rdctl = W_op_opx & (W_iw_opx == 38);
|
394 |
|
|
assign W_op_mul = W_op_opx & (W_iw_opx == 39);
|
395 |
|
|
assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40);
|
396 |
|
|
assign W_op_initi = W_op_opx & (W_iw_opx == 41);
|
397 |
|
|
assign W_op_trap = W_op_opx & (W_iw_opx == 45);
|
398 |
|
|
assign W_op_wrctl = W_op_opx & (W_iw_opx == 46);
|
399 |
|
|
assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48);
|
400 |
|
|
assign W_op_add = W_op_opx & (W_iw_opx == 49);
|
401 |
|
|
assign W_op_break = W_op_opx & (W_iw_opx == 52);
|
402 |
|
|
assign W_op_hbreak = W_op_opx & (W_iw_opx == 53);
|
403 |
|
|
assign W_op_sync = W_op_opx & (W_iw_opx == 54);
|
404 |
|
|
assign W_op_sub = W_op_opx & (W_iw_opx == 57);
|
405 |
|
|
assign W_op_srai = W_op_opx & (W_iw_opx == 58);
|
406 |
|
|
assign W_op_sra = W_op_opx & (W_iw_opx == 59);
|
407 |
|
|
assign W_op_intr = W_op_opx & (W_iw_opx == 61);
|
408 |
|
|
assign W_op_crst = W_op_opx & (W_iw_opx == 62);
|
409 |
|
|
assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0);
|
410 |
|
|
assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10);
|
411 |
|
|
assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15);
|
412 |
|
|
assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17);
|
413 |
|
|
assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21);
|
414 |
|
|
assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25);
|
415 |
|
|
assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33);
|
416 |
|
|
assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34);
|
417 |
|
|
assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35);
|
418 |
|
|
assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42);
|
419 |
|
|
assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43);
|
420 |
|
|
assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44);
|
421 |
|
|
assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47);
|
422 |
|
|
assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50);
|
423 |
|
|
assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51);
|
424 |
|
|
assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55);
|
425 |
|
|
assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56);
|
426 |
|
|
assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60);
|
427 |
|
|
assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63);
|
428 |
|
|
assign W_op_opx = W_iw_op == 58;
|
429 |
|
|
assign W_op_custom = W_iw_op == 50;
|
430 |
|
|
always @(posedge clk or negedge reset_n)
|
431 |
|
|
begin
|
432 |
|
|
if (reset_n == 0)
|
433 |
|
|
A_target_pcb <= 0;
|
434 |
|
|
else if (A_en)
|
435 |
|
|
A_target_pcb <= M_target_pcb;
|
436 |
|
|
end
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
always @(posedge clk or negedge reset_n)
|
440 |
|
|
begin
|
441 |
|
|
if (reset_n == 0)
|
442 |
|
|
A_mem_baddr <= 0;
|
443 |
|
|
else if (A_en)
|
444 |
|
|
A_mem_baddr <= M_mem_baddr;
|
445 |
|
|
end
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
assign E_src1_eq_src2 = E_logic_result == 0;
|
449 |
|
|
//Propagating 'X' data bits
|
450 |
|
|
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
|
451 |
|
|
|
452 |
|
|
//Propagating 'X' data bits
|
453 |
|
|
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
|
454 |
|
|
|
455 |
|
|
//Propagating 'X' data bits
|
456 |
|
|
assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
|
457 |
|
|
|
458 |
|
|
//Propagating 'X' data bits
|
459 |
|
|
assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
|
460 |
|
|
|
461 |
|
|
assign test_has_ended = 1'b0;
|
462 |
|
|
|
463 |
|
|
//synthesis translate_off
|
464 |
|
|
//////////////// SIMULATION-ONLY CONTENTS
|
465 |
|
|
//Clearing 'X' data bits
|
466 |
|
|
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
|
467 |
|
|
|
468 |
|
|
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
|
469 |
|
|
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
|
470 |
|
|
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
|
471 |
|
|
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
|
472 |
|
|
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
|
473 |
|
|
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
|
474 |
|
|
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
|
475 |
|
|
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
|
476 |
|
|
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
|
477 |
|
|
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
|
478 |
|
|
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
|
479 |
|
|
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
|
480 |
|
|
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
|
481 |
|
|
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
|
482 |
|
|
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
|
483 |
|
|
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
|
484 |
|
|
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
|
485 |
|
|
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
|
486 |
|
|
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
|
487 |
|
|
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
|
488 |
|
|
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
|
489 |
|
|
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
|
490 |
|
|
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
|
491 |
|
|
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
|
492 |
|
|
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
|
493 |
|
|
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
|
494 |
|
|
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
|
495 |
|
|
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
|
496 |
|
|
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
|
497 |
|
|
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
|
498 |
|
|
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
|
499 |
|
|
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
|
500 |
|
|
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
|
501 |
|
|
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
|
502 |
|
|
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
|
503 |
|
|
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
|
504 |
|
|
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
|
505 |
|
|
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
|
506 |
|
|
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
|
507 |
|
|
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
|
508 |
|
|
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
|
509 |
|
|
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
|
510 |
|
|
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
|
511 |
|
|
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
|
512 |
|
|
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
|
513 |
|
|
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
|
514 |
|
|
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
|
515 |
|
|
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
|
516 |
|
|
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
|
517 |
|
|
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
|
518 |
|
|
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
|
519 |
|
|
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
|
520 |
|
|
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
|
521 |
|
|
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
|
522 |
|
|
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
|
523 |
|
|
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
|
524 |
|
|
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
|
525 |
|
|
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
|
526 |
|
|
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
|
527 |
|
|
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
|
528 |
|
|
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
|
529 |
|
|
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
|
530 |
|
|
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
|
531 |
|
|
always @(posedge clk)
|
532 |
|
|
begin
|
533 |
|
|
if (reset_n)
|
534 |
|
|
if (^(W_wr_dst_reg) === 1'bx)
|
535 |
|
|
begin
|
536 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/W_wr_dst_reg is 'x'\n", $time);
|
537 |
|
|
$stop;
|
538 |
|
|
end
|
539 |
|
|
end
|
540 |
|
|
|
541 |
|
|
|
542 |
|
|
always @(posedge clk or negedge reset_n)
|
543 |
|
|
begin
|
544 |
|
|
if (reset_n == 0)
|
545 |
|
|
begin
|
546 |
|
|
end
|
547 |
|
|
else if (W_wr_dst_reg)
|
548 |
|
|
if (^(W_dst_regnum) === 1'bx)
|
549 |
|
|
begin
|
550 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/W_dst_regnum is 'x'\n", $time);
|
551 |
|
|
$stop;
|
552 |
|
|
end
|
553 |
|
|
end
|
554 |
|
|
|
555 |
|
|
|
556 |
|
|
always @(posedge clk)
|
557 |
|
|
begin
|
558 |
|
|
if (reset_n)
|
559 |
|
|
if (^(W_valid) === 1'bx)
|
560 |
|
|
begin
|
561 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/W_valid is 'x'\n", $time);
|
562 |
|
|
$stop;
|
563 |
|
|
end
|
564 |
|
|
end
|
565 |
|
|
|
566 |
|
|
|
567 |
|
|
always @(posedge clk or negedge reset_n)
|
568 |
|
|
begin
|
569 |
|
|
if (reset_n == 0)
|
570 |
|
|
begin
|
571 |
|
|
end
|
572 |
|
|
else if (W_valid)
|
573 |
|
|
if (^(W_pcb) === 1'bx)
|
574 |
|
|
begin
|
575 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/W_pcb is 'x'\n", $time);
|
576 |
|
|
$stop;
|
577 |
|
|
end
|
578 |
|
|
end
|
579 |
|
|
|
580 |
|
|
|
581 |
|
|
always @(posedge clk or negedge reset_n)
|
582 |
|
|
begin
|
583 |
|
|
if (reset_n == 0)
|
584 |
|
|
begin
|
585 |
|
|
end
|
586 |
|
|
else if (W_valid)
|
587 |
|
|
if (^(W_iw) === 1'bx)
|
588 |
|
|
begin
|
589 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/W_iw is 'x'\n", $time);
|
590 |
|
|
$stop;
|
591 |
|
|
end
|
592 |
|
|
end
|
593 |
|
|
|
594 |
|
|
|
595 |
|
|
always @(posedge clk)
|
596 |
|
|
begin
|
597 |
|
|
if (reset_n)
|
598 |
|
|
if (^(A_en) === 1'bx)
|
599 |
|
|
begin
|
600 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/A_en is 'x'\n", $time);
|
601 |
|
|
$stop;
|
602 |
|
|
end
|
603 |
|
|
end
|
604 |
|
|
|
605 |
|
|
|
606 |
|
|
always @(posedge clk)
|
607 |
|
|
begin
|
608 |
|
|
if (reset_n)
|
609 |
|
|
if (^(E_valid) === 1'bx)
|
610 |
|
|
begin
|
611 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/E_valid is 'x'\n", $time);
|
612 |
|
|
$stop;
|
613 |
|
|
end
|
614 |
|
|
end
|
615 |
|
|
|
616 |
|
|
|
617 |
|
|
always @(posedge clk)
|
618 |
|
|
begin
|
619 |
|
|
if (reset_n)
|
620 |
|
|
if (^(M_valid) === 1'bx)
|
621 |
|
|
begin
|
622 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/M_valid is 'x'\n", $time);
|
623 |
|
|
$stop;
|
624 |
|
|
end
|
625 |
|
|
end
|
626 |
|
|
|
627 |
|
|
|
628 |
|
|
always @(posedge clk)
|
629 |
|
|
begin
|
630 |
|
|
if (reset_n)
|
631 |
|
|
if (^(A_valid) === 1'bx)
|
632 |
|
|
begin
|
633 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/A_valid is 'x'\n", $time);
|
634 |
|
|
$stop;
|
635 |
|
|
end
|
636 |
|
|
end
|
637 |
|
|
|
638 |
|
|
|
639 |
|
|
always @(posedge clk or negedge reset_n)
|
640 |
|
|
begin
|
641 |
|
|
if (reset_n == 0)
|
642 |
|
|
begin
|
643 |
|
|
end
|
644 |
|
|
else if (A_valid & A_en & A_wr_dst_reg)
|
645 |
|
|
if (^(A_wr_data_unfiltered) === 1'bx)
|
646 |
|
|
begin
|
647 |
|
|
$write("%0d ns: WARNING: cpu_0_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
|
648 |
|
|
end
|
649 |
|
|
end
|
650 |
|
|
|
651 |
|
|
|
652 |
|
|
always @(posedge clk)
|
653 |
|
|
begin
|
654 |
|
|
if (reset_n)
|
655 |
|
|
if (^(A_status_reg) === 1'bx)
|
656 |
|
|
begin
|
657 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/A_status_reg is 'x'\n", $time);
|
658 |
|
|
$stop;
|
659 |
|
|
end
|
660 |
|
|
end
|
661 |
|
|
|
662 |
|
|
|
663 |
|
|
always @(posedge clk)
|
664 |
|
|
begin
|
665 |
|
|
if (reset_n)
|
666 |
|
|
if (^(A_estatus_reg) === 1'bx)
|
667 |
|
|
begin
|
668 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/A_estatus_reg is 'x'\n", $time);
|
669 |
|
|
$stop;
|
670 |
|
|
end
|
671 |
|
|
end
|
672 |
|
|
|
673 |
|
|
|
674 |
|
|
always @(posedge clk)
|
675 |
|
|
begin
|
676 |
|
|
if (reset_n)
|
677 |
|
|
if (^(A_bstatus_reg) === 1'bx)
|
678 |
|
|
begin
|
679 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/A_bstatus_reg is 'x'\n", $time);
|
680 |
|
|
$stop;
|
681 |
|
|
end
|
682 |
|
|
end
|
683 |
|
|
|
684 |
|
|
|
685 |
|
|
always @(posedge clk)
|
686 |
|
|
begin
|
687 |
|
|
if (reset_n)
|
688 |
|
|
if (^(i_read) === 1'bx)
|
689 |
|
|
begin
|
690 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/i_read is 'x'\n", $time);
|
691 |
|
|
$stop;
|
692 |
|
|
end
|
693 |
|
|
end
|
694 |
|
|
|
695 |
|
|
|
696 |
|
|
always @(posedge clk or negedge reset_n)
|
697 |
|
|
begin
|
698 |
|
|
if (reset_n == 0)
|
699 |
|
|
begin
|
700 |
|
|
end
|
701 |
|
|
else if (i_read)
|
702 |
|
|
if (^(i_address) === 1'bx)
|
703 |
|
|
begin
|
704 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/i_address is 'x'\n", $time);
|
705 |
|
|
$stop;
|
706 |
|
|
end
|
707 |
|
|
end
|
708 |
|
|
|
709 |
|
|
|
710 |
|
|
always @(posedge clk)
|
711 |
|
|
begin
|
712 |
|
|
if (reset_n)
|
713 |
|
|
if (^(i_readdatavalid) === 1'bx)
|
714 |
|
|
begin
|
715 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/i_readdatavalid is 'x'\n", $time);
|
716 |
|
|
$stop;
|
717 |
|
|
end
|
718 |
|
|
end
|
719 |
|
|
|
720 |
|
|
|
721 |
|
|
always @(posedge clk)
|
722 |
|
|
begin
|
723 |
|
|
if (reset_n)
|
724 |
|
|
if (^(d_write) === 1'bx)
|
725 |
|
|
begin
|
726 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/d_write is 'x'\n", $time);
|
727 |
|
|
$stop;
|
728 |
|
|
end
|
729 |
|
|
end
|
730 |
|
|
|
731 |
|
|
|
732 |
|
|
always @(posedge clk or negedge reset_n)
|
733 |
|
|
begin
|
734 |
|
|
if (reset_n == 0)
|
735 |
|
|
begin
|
736 |
|
|
end
|
737 |
|
|
else if (d_write)
|
738 |
|
|
if (^(d_byteenable) === 1'bx)
|
739 |
|
|
begin
|
740 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/d_byteenable is 'x'\n", $time);
|
741 |
|
|
$stop;
|
742 |
|
|
end
|
743 |
|
|
end
|
744 |
|
|
|
745 |
|
|
|
746 |
|
|
always @(posedge clk or negedge reset_n)
|
747 |
|
|
begin
|
748 |
|
|
if (reset_n == 0)
|
749 |
|
|
begin
|
750 |
|
|
end
|
751 |
|
|
else if (d_write | d_read)
|
752 |
|
|
if (^(d_address) === 1'bx)
|
753 |
|
|
begin
|
754 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/d_address is 'x'\n", $time);
|
755 |
|
|
$stop;
|
756 |
|
|
end
|
757 |
|
|
end
|
758 |
|
|
|
759 |
|
|
|
760 |
|
|
always @(posedge clk)
|
761 |
|
|
begin
|
762 |
|
|
if (reset_n)
|
763 |
|
|
if (^(d_read) === 1'bx)
|
764 |
|
|
begin
|
765 |
|
|
$write("%0d ns: ERROR: cpu_0_test_bench/d_read is 'x'\n", $time);
|
766 |
|
|
$stop;
|
767 |
|
|
end
|
768 |
|
|
end
|
769 |
|
|
|
770 |
|
|
|
771 |
|
|
|
772 |
|
|
reg [31:0] trace_handle; // for $fopen
|
773 |
|
|
initial
|
774 |
|
|
begin
|
775 |
|
|
trace_handle = $fopen("cpu_0.tr");
|
776 |
|
|
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
|
777 |
|
|
end
|
778 |
|
|
always @(posedge clk)
|
779 |
|
|
begin
|
780 |
|
|
if ((~reset_n || (A_valid & A_en)) && ~test_has_ended)
|
781 |
|
|
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, A_pcb, 0, A_op_intr, A_op_hbreak, A_iw, ~(A_op_intr | A_op_hbreak), A_wr_dst_reg, A_dst_regnum, 0, A_wr_data_filtered, A_mem_baddr, A_st_data, A_mem_byte_en, A_cmp_result, A_target_pcb, A_status_reg, A_estatus_reg, A_bstatus_reg, A_ienable_reg, A_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, A_ctrl_exception ? 1 : 0, 0, 0, 0, 0);
|
782 |
|
|
end
|
783 |
|
|
|
784 |
|
|
|
785 |
|
|
|
786 |
|
|
//////////////// END SIMULATION-ONLY CONTENTS
|
787 |
|
|
|
788 |
|
|
//synthesis translate_on
|
789 |
|
|
//synthesis read_comments_as_HDL on
|
790 |
|
|
//
|
791 |
|
|
// assign A_wr_data_filtered = A_wr_data_unfiltered;
|
792 |
|
|
//
|
793 |
|
|
//synthesis read_comments_as_HDL off
|
794 |
|
|
|
795 |
|
|
endmodule
|
796 |
|
|
|