1 |
147 |
lanttu |
-------------------------------------------------------------------------------
|
2 |
|
|
-- Title : HIBI PE DMA - top level
|
3 |
|
|
-- Project :
|
4 |
|
|
-------------------------------------------------------------------------------
|
5 |
|
|
-- File : hibi_pe_dma.vhd
|
6 |
|
|
-- Author : kulmala3
|
7 |
|
|
-- Created : 2011-04-04
|
8 |
|
|
-- Last update: 2012-02-08
|
9 |
|
|
-- Description:
|
10 |
|
|
-------------------------------------------------------------------------------
|
11 |
|
|
-- Copyright (c) 2005
|
12 |
|
|
-------------------------------------------------------------------------------
|
13 |
|
|
-- Revisions :
|
14 |
|
|
-- Date Version Author Description
|
15 |
|
|
-- 30.03.2005 1.0 AK Created
|
16 |
|
|
-------------------------------------------------------------------------------
|
17 |
|
|
library ieee;
|
18 |
|
|
use ieee.std_logic_1164.all;
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
entity hibi_pe_dma is
|
22 |
|
|
|
23 |
|
|
generic (
|
24 |
|
|
data_width_g : integer := 32; -- 32 and 64 supported
|
25 |
|
|
addr_width_g : integer := 32;
|
26 |
|
|
words_width_g : integer := 16;
|
27 |
|
|
n_stream_chans_g : integer := 4; -- how many streaming channels
|
28 |
|
|
n_packet_chans_g : integer := 4; -- how many packet channels
|
29 |
|
|
n_chans_bits_g : integer := 3; -- how many bits to show all channels
|
30 |
|
|
-- eg 2 for 4, 3 for 5, basically log2(n_packet_chans_g+n_stream_chans_g)
|
31 |
|
|
hibi_addr_cmp_lo_g : integer := 8;
|
32 |
|
|
hibi_addr_cmp_hi_g : integer := 31
|
33 |
|
|
);
|
34 |
|
|
|
35 |
|
|
port (
|
36 |
|
|
clk : in std_logic;
|
37 |
|
|
rst_n : in std_logic;
|
38 |
|
|
|
39 |
|
|
-- avalon master (rx) if
|
40 |
|
|
avalon_addr_out_rx : out std_logic_vector(addr_width_g-1 downto 0);
|
41 |
|
|
avalon_we_out_rx : out std_logic;
|
42 |
|
|
avalon_be_out_rx : out std_logic_vector(data_width_g/8-1 downto 0);
|
43 |
|
|
avalon_writedata_out_rx : out std_logic_vector(data_width_g-1 downto 0);
|
44 |
|
|
avalon_waitrequest_in_rx : in std_logic;
|
45 |
|
|
|
46 |
|
|
--avalon slave if (config)
|
47 |
|
|
avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0);
|
48 |
|
|
avalon_cfg_writedata_in : in std_logic_vector(addr_width_g-1 downto 0);
|
49 |
|
|
avalon_cfg_we_in : in std_logic;
|
50 |
|
|
avalon_cfg_readdata_out : out std_logic_vector(addr_width_g-1 downto 0);
|
51 |
|
|
avalon_cfg_re_in : in std_logic;
|
52 |
|
|
avalon_cfg_cs_in : in std_logic;
|
53 |
|
|
avalon_cfg_waitrequest_out : out std_logic;
|
54 |
|
|
|
55 |
|
|
-- Avalon master read interface (tx)
|
56 |
|
|
avalon_addr_out_tx : out std_logic_vector(addr_width_g-1 downto 0);
|
57 |
|
|
avalon_re_out_tx : out std_logic;
|
58 |
|
|
avalon_readdata_in_tx : in std_logic_vector(data_width_g-1 downto 0);
|
59 |
|
|
avalon_waitrequest_in_tx : in std_logic;
|
60 |
|
|
avalon_readdatavalid_in_tx : in std_logic;
|
61 |
|
|
|
62 |
|
|
-- hibi (rx) if
|
63 |
|
|
hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
|
64 |
|
|
hibi_av_in : in std_logic;
|
65 |
|
|
hibi_empty_in : in std_logic;
|
66 |
|
|
hibi_comm_in : in std_logic_vector(4 downto 0);
|
67 |
|
|
hibi_re_out : out std_logic;
|
68 |
|
|
|
69 |
|
|
-- hibi write interface (tx)
|
70 |
|
|
hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
|
71 |
|
|
hibi_av_out : out std_logic;
|
72 |
|
|
hibi_full_in : in std_logic;
|
73 |
|
|
hibi_comm_out : out std_logic_vector(4 downto 0);
|
74 |
|
|
hibi_we_out : out std_logic;
|
75 |
|
|
|
76 |
|
|
rx_irq_out : out std_logic
|
77 |
|
|
|
78 |
|
|
);
|
79 |
|
|
|
80 |
|
|
end hibi_pe_dma;
|
81 |
|
|
|
82 |
|
|
|
83 |
|
|
|
84 |
|
|
architecture structural of hibi_pe_dma is
|
85 |
|
|
|
86 |
|
|
signal tx_start_from_rx : std_logic;
|
87 |
|
|
signal tx_comm_from_rx : std_logic_vector(4 downto 0);
|
88 |
|
|
signal tx_mem_addr_from_rx : std_logic_vector(addr_width_g-1 downto 0);
|
89 |
|
|
signal tx_hibi_addr_from_rx : std_logic_vector(addr_width_g-1 downto 0);
|
90 |
|
|
signal tx_words_from_rx : std_logic_vector(words_width_g-1 downto 0);
|
91 |
|
|
signal tx_status_done_to_rx : std_logic;
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
begin -- structural
|
95 |
|
|
|
96 |
|
|
assert data_width_g = 64 or data_width_g = 32
|
97 |
|
|
report "Data width other than 32 or 64 not currently supported"
|
98 |
|
|
severity failure;
|
99 |
|
|
|
100 |
|
|
rx_conf : entity work.hpd_rx_and_conf
|
101 |
|
|
generic map (
|
102 |
|
|
n_stream_chans_g => n_stream_chans_g,
|
103 |
|
|
n_packet_chans_g => n_packet_chans_g,
|
104 |
|
|
n_chans_bits_g => n_chans_bits_g,
|
105 |
|
|
data_width_g => data_width_g,
|
106 |
|
|
addr_width_g => addr_width_g,
|
107 |
|
|
hibi_addr_cmp_hi_g => hibi_addr_cmp_hi_g,
|
108 |
|
|
hibi_addr_cmp_lo_g => hibi_addr_cmp_lo_g,
|
109 |
|
|
words_width_g => words_width_g
|
110 |
|
|
)
|
111 |
|
|
port map (
|
112 |
|
|
clk => clk,
|
113 |
|
|
rst_n => rst_n,
|
114 |
|
|
avalon_addr_out => avalon_addr_out_rx,
|
115 |
|
|
avalon_we_out => avalon_we_out_rx,
|
116 |
|
|
avalon_be_out => avalon_be_out_rx,
|
117 |
|
|
avalon_writedata_out => avalon_writedata_out_rx,
|
118 |
|
|
avalon_waitrequest_in => avalon_waitrequest_in_rx,
|
119 |
|
|
hibi_data_in => hibi_data_in,
|
120 |
|
|
hibi_av_in => hibi_av_in,
|
121 |
|
|
hibi_empty_in => hibi_empty_in,
|
122 |
|
|
hibi_comm_in => hibi_comm_in,
|
123 |
|
|
hibi_re_out => hibi_re_out,
|
124 |
|
|
avalon_cfg_addr_in => avalon_cfg_addr_in,
|
125 |
|
|
avalon_cfg_writedata_in => avalon_cfg_writedata_in,
|
126 |
|
|
avalon_cfg_we_in => avalon_cfg_we_in,
|
127 |
|
|
avalon_cfg_readdata_out => avalon_cfg_readdata_out,
|
128 |
|
|
avalon_cfg_re_in => avalon_cfg_re_in,
|
129 |
|
|
avalon_cfg_cs_in => avalon_cfg_cs_in,
|
130 |
|
|
avalon_cfg_waitrequest_out => avalon_cfg_waitrequest_out,
|
131 |
|
|
rx_irq_out => rx_irq_out,
|
132 |
|
|
tx_start_out => tx_start_from_rx,
|
133 |
|
|
tx_comm_out => tx_comm_from_rx,
|
134 |
|
|
tx_mem_addr_out => tx_mem_addr_from_rx,
|
135 |
|
|
tx_hibi_addr_out => tx_hibi_addr_from_rx,
|
136 |
|
|
tx_words_out => tx_words_from_rx,
|
137 |
|
|
tx_status_done_in => tx_status_done_to_rx
|
138 |
|
|
);
|
139 |
|
|
|
140 |
|
|
tx_control : entity work.hpd_tx_control
|
141 |
|
|
generic map (
|
142 |
|
|
data_width_g => data_width_g,
|
143 |
|
|
addr_width_g => addr_width_g,
|
144 |
|
|
words_width_g => words_width_g)
|
145 |
|
|
port map (
|
146 |
|
|
clk => clk,
|
147 |
|
|
rst_n => rst_n,
|
148 |
|
|
avalon_addr_out => avalon_addr_out_tx,
|
149 |
|
|
avalon_re_out => avalon_re_out_tx,
|
150 |
|
|
avalon_readdata_in => avalon_readdata_in_tx,
|
151 |
|
|
avalon_waitrequest_in => avalon_waitrequest_in_tx,
|
152 |
|
|
avalon_readdatavalid_in => avalon_readdatavalid_in_tx,
|
153 |
|
|
hibi_data_out => hibi_data_out,
|
154 |
|
|
hibi_av_out => hibi_av_out,
|
155 |
|
|
hibi_full_in => hibi_full_in,
|
156 |
|
|
hibi_comm_out => hibi_comm_out,
|
157 |
|
|
hibi_we_out => hibi_we_out,
|
158 |
|
|
tx_start_in => tx_start_from_rx,
|
159 |
|
|
tx_status_done_out => tx_status_done_to_rx,
|
160 |
|
|
tx_hibi_addr_in => tx_hibi_addr_from_rx,
|
161 |
|
|
tx_comm_in => tx_comm_from_rx,
|
162 |
|
|
tx_ram_addr_in => tx_mem_addr_from_rx,
|
163 |
|
|
tx_words_in => tx_words_from_rx
|
164 |
|
|
);
|
165 |
|
|
|
166 |
|
|
end structural;
|