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-------------------------------------------------------------------------------
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-- Title : HIBI PE DMA - rx and configuration
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-- Project :
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-------------------------------------------------------------------------------
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-- File : hpd_rx_and_conf.vhd
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-- Author : kulmala3
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-- Created : 2012-01-10
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-- Last update: 2012-03-02
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-- Description:
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--
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-- Currently there's no double-registers in config - the user
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-- must take care when configuring the device. (datas can go to
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-- wrong address etc, if configured while still receiving data from
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-- source)
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--
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-- Needs 2 clock cycles to propagate the IRQ (ack->irq down-> irq req)
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-------------------------------------------------------------------------------
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-- Copyright (c) 2005
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 22.03.2005 1.0 AK Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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entity hpd_rx_and_conf is
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generic (
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n_stream_chans_g : integer := 4; -- how many streaming channels
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n_packet_chans_g : integer := 4;
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n_chans_bits_g : integer := 2; -- how many bits to represent n_chans
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-- and n_streams
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-- eg 2 for 4, 3 for 5, basically
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-- log2(n_packet_chans_g)
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data_width_g : integer := 1;
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addr_width_g : integer := 1; -- the memory addr width
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hibi_addr_cmp_hi_g : integer := 1; -- the highest bit used for comparing
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hibi_addr_cmp_lo_g : integer := 1; -- the lowest bit
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words_width_g : integer := 1); -- in bits, maximum amount of data
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-- supposes that words is always in 32 bit words!
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-- (due to Nios II 32-bitness)
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- avalon master (rx) if
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avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0);
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avalon_we_out : out std_logic;
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avalon_be_out : out std_logic_vector(data_width_g/8-1 downto 0);
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avalon_writedata_out : out std_logic_vector(data_width_g-1 downto 0);
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avalon_waitrequest_in : in std_logic;
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-- hibi if
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hibi_data_in : in std_logic_vector(data_width_g-1 downto 0);
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hibi_av_in : in std_logic;
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hibi_empty_in : in std_logic;
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hibi_comm_in : in std_logic_vector(4 downto 0);
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hibi_re_out : out std_logic;
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--avalon slave if (config)
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--conf_bits_c bits for each channel
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avalon_cfg_addr_in : in std_logic_vector(n_chans_bits_g+4-1 downto 0);
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avalon_cfg_writedata_in : in std_logic_vector(addr_width_g-1 downto 0);
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avalon_cfg_we_in : in std_logic;
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avalon_cfg_readdata_out : out std_logic_vector(addr_width_g-1 downto 0);
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avalon_cfg_re_in : in std_logic;
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avalon_cfg_cs_in : in std_logic;
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avalon_cfg_waitrequest_out : out std_logic;
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rx_irq_out : out std_logic;
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-- to/from tx
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tx_start_out : out std_logic;
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tx_comm_out : out std_logic_vector(4 downto 0);
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tx_mem_addr_out : out std_logic_vector(addr_width_g-1 downto 0);
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tx_hibi_addr_out : out std_logic_vector(addr_width_g-1 downto 0);
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tx_words_out : out std_logic_vector(words_width_g-1 downto 0);
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tx_status_done_in : in std_logic
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);
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end hpd_rx_and_conf;
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architecture rtl of hpd_rx_and_conf is
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-- NOTE!! Also have to change to interface!! avalon_cfg_addr_in !!!
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constant conf_bits_c : integer := 4; -- number of configuration bits in
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-- CPU side address
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constant control_bits_c : integer := 2; -- how many bits in ctrl reg
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constant status_bits_c : integer := 2; -- how many bits in ctrl reg
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constant addr_offset_c : integer := data_width_g/8;
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constant be_width_c : integer := data_width_g/8;
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constant total_channels_c : integer := n_stream_chans_g + n_packet_chans_g;
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constant hibi_addr_width_c : integer := addr_width_g;
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type chan_addr_array is array (total_channels_c-1 downto 0)
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of std_logic_vector(addr_width_g-1 downto 0);
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type chan_be_array is array (total_channels_c-1 downto 0)
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of std_logic_vector(be_width_c-1 downto 0);
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type chan_words_array is array (total_channels_c-1 downto 0)
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of std_logic_vector(words_width_g-1 downto 0);
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type rx_words_array is array (total_channels_c-1 downto 0)
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of std_logic_vector(words_width_g-1 downto 0);
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-- registers the CPU will set
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signal mem_addr_r : chan_addr_array;
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signal sender_addr_r : chan_addr_array;
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signal irq_words_r : chan_words_array;
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signal rx_words : rx_words_array;
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signal read_ack_r : std_logic_vector(n_stream_chans_g-1 downto 0);
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signal control_r : std_logic_vector(control_bits_c-1 downto 0);
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signal tx_mem_addr_r : std_logic_vector(addr_width_g-1 downto 0);
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signal tx_hibi_addr_r : std_logic_vector(hibi_addr_width_c-1 downto 0);
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signal tx_words_r : std_logic_vector(words_width_g-1 downto 0);
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signal tx_comm_r : std_logic_vector(4 downto 0);
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-- cpu sets, hpd clears
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signal init_chan_r : std_logic_vector(total_channels_c-1 downto 0);
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signal irq_chan_r : std_logic_vector(total_channels_c-1 downto 0);
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signal irq_type_r : std_logic; -- 0: rx ready, 1: unknown rx
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-- cpu can read
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-- tells where the next data is stored
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signal current_mem_addr_r : chan_addr_array;
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signal current_be_r : chan_be_array;
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signal avalon_be : std_logic_vector(be_width_c-1 downto 0);
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signal status_r : std_logic_vector(status_bits_c-1 downto 0);
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-- counter of how many datas gotten (irq nullifies)
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signal irq_counter_r : chan_words_array;
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signal irq_r : std_logic;
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signal irq_given_r : std_logic_vector(total_channels_c-1 downto 0);
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signal irq_reset_r : std_logic; -- irq was reseted last cycle
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signal was_high_r : std_logic;
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signal hibi_re : std_logic;
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signal avalon_we : std_logic;
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signal unknown_rx : std_logic; -- high when not expecting this rx
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signal unknown_rx_irq_r : std_logic;
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signal unknown_rx_r : std_logic;
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-- high when tx is overriding previous one
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-- (user didn't poll if previous tx is still in progress)
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signal tx_illegal : std_logic;
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signal tx_illegal_r : std_logic;
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signal ignore_tx_write : std_logic;
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signal ignored_last_tx_r : std_logic;
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-- calc_chan signals
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signal avalon_addr : std_logic_vector(addr_width_g-1 downto 0);
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signal curr_chan_avalon_we_r : std_logic; -- 0 if no channel found
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signal avalon_wes : std_logic_vector(total_channels_c-1 downto 0);
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signal matches : std_logic_vector(total_channels_c-1 downto 0);
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signal matches_cmb : std_logic_vector(total_channels_c-1 downto 0);
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signal irq_ack_r : std_logic_vector(total_channels_c-1 downto 0);
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type chan_addr_switched is array (addr_width_g-1 downto 0)
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of std_logic_vector(total_channels_c-1 downto 0);
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type chan_be_switched is array (be_width_c-1 downto 0)
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of std_logic_vector(total_channels_c-1 downto 0);
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signal avalon_addr_temp : chan_addr_switched;
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signal avalon_be_temp : chan_be_switched;
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signal avalon_cfg_waitrequest_out_r : std_logic;
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signal avalon_cfg_waitrequest_out_s : std_logic;
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signal cfg_write : std_logic;
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signal cfg_reg : integer range (2**conf_bits_c)-1 downto 0;
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-- high when tx conf registers (8-11) are being written
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signal cfg_tx_reg_used : std_logic;
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begin -- rtl
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-----------------------------------------------------------------------------
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-- Handle waitrequest for config interface
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-----------------------------------------------------------------------------
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avalon_cfg_waitrequest_out <= avalon_cfg_waitrequest_out_s;
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cfg_write <= avalon_cfg_we_in and avalon_cfg_cs_in;
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avalon_cfg_waitrequest_out_s <= ((not avalon_cfg_waitrequest_out_r)
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and avalon_cfg_re_in
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and avalon_cfg_cs_in);
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wait_p : process (clk, rst_n)
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begin -- process wait_p
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if rst_n = '0' then -- asynchronous reset (active low)
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avalon_cfg_waitrequest_out_r <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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avalon_cfg_waitrequest_out_r <= avalon_cfg_waitrequest_out_s;
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end if;
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end process wait_p;
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-----------------------------------------------------------------------------
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-- Handle txs, dismiss tx if previous one is still in progress
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-----------------------------------------------------------------------------
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cfg_reg <= conv_integer(avalon_cfg_addr_in(conf_bits_c-1 downto 0));
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cfg_tx_p : process (cfg_reg)
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begin -- process cfg_tx_p
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case cfg_reg is
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when 8 | 9 | 10 | 11 => cfg_tx_reg_used <= '1';
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when others => cfg_tx_reg_used <= '0';
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end case;
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end process cfg_tx_p;
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tx_illegal <= (not tx_status_done_in) and cfg_tx_reg_used and cfg_write;
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tx_illegal_p : process (clk, rst_n)
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begin -- process tx_illegal_p
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if rst_n = '0' then -- asynchronous reset (active low)
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tx_illegal_r <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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if tx_illegal_r = '0' then
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tx_illegal_r <= tx_illegal;
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elsif tx_illegal_r = '1' and cfg_reg = 4 and cfg_tx_reg_used = '1'
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and cfg_write = '1'
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then
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tx_illegal_r <= '0';
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elsif cfg_reg = 7 and cfg_write = '1'
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and avalon_cfg_writedata_in(data_width_g-2) = '1'
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then
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tx_illegal_r <= '0';
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else
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tx_illegal_r <= '1';
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end if;
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end if;
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end process tx_illegal_p;
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ignore_tx_write <= tx_illegal or tx_illegal_r;
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-----------------------------------------------------------------------------
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-- Rest of the stuff
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-----------------------------------------------------------------------------
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avalon_we <= hibi_empty_in nor hibi_av_in;
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avalon_we_out <= avalon_we and curr_chan_avalon_we_r;
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hibi_re <= (not avalon_waitrequest_in or hibi_av_in) -- three first were just anded
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and (avalon_we or hibi_empty_in or hibi_av_in)
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and (curr_chan_avalon_we_r or hibi_empty_in)
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and not (unknown_rx or unknown_rx_irq_r);
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unknown_rx <= (not or_reduce(matches_cmb) and
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(hibi_av_in and not hibi_empty_in));
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hibi_re_out <= hibi_re and not unknown_rx;
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avalon_writedata_out <= hibi_data_in;
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avalon_addr_out <= avalon_addr;
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avalon_be_out <= avalon_be;
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stream_channels : for i in 0 to n_stream_chans_g-1 generate
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rx_stream : entity work.hpd_rx_stream
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generic map (
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data_width_g => data_width_g,
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hibi_addr_width_g => hibi_addr_width_c,
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addr_width_g => addr_width_g,
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words_width_g => words_width_g,
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addr_cmp_lo_g => hibi_addr_cmp_lo_g,
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addr_cmp_hi_g => hibi_addr_cmp_hi_g)
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port map (
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clk => clk,
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rst_n => rst_n,
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avalon_addr_in => mem_addr_r(i),
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hibi_addr_in => sender_addr_r(i),
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irq_words_in => irq_words_r(i),
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hibi_data_in => hibi_data_in(hibi_addr_width_c-1 downto 0),
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hibi_av_in => hibi_av_in,
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hibi_empty_in => hibi_empty_in,
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init_in => init_chan_r(i),
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irq_ack_in => irq_ack_r(i),
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avalon_waitreq_in => avalon_waitrequest_in,
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avalon_we_in => avalon_we,
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avalon_addr_out => current_mem_addr_r(i),
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avalon_we_out => avalon_wes(i),
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avalon_be_out => current_be_r(i),
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addr_match_out => matches(i),
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addr_match_cmb_out => matches_cmb(i),
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irq_out => irq_chan_r(i),
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words_out => rx_words(i),
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read_ack_in => read_ack_r(i)
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);
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end generate stream_channels;
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packet_channels : for i in n_stream_chans_g to n_stream_chans_g + n_packet_chans_g - 1 generate
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rx_packet : entity work.hpd_rx_packet
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generic map (
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data_width_g => data_width_g,
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hibi_addr_width_g => hibi_addr_width_c,
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addr_width_g => addr_width_g,
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words_width_g => words_width_g,
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319 |
|
|
addr_cmp_lo_g => hibi_addr_cmp_lo_g,
|
320 |
|
|
addr_cmp_hi_g => hibi_addr_cmp_hi_g)
|
321 |
|
|
port map (
|
322 |
|
|
clk => clk,
|
323 |
|
|
rst_n => rst_n,
|
324 |
|
|
avalon_addr_in => mem_addr_r(i),
|
325 |
|
|
hibi_addr_in => sender_addr_r(i),
|
326 |
|
|
irq_words_in => irq_words_r(i),
|
327 |
|
|
hibi_data_in => hibi_data_in(hibi_addr_width_c-1 downto 0),
|
328 |
|
|
hibi_av_in => hibi_av_in,
|
329 |
|
|
hibi_empty_in => hibi_empty_in,
|
330 |
|
|
init_in => init_chan_r(i),
|
331 |
|
|
irq_ack_in => irq_ack_r(i),
|
332 |
|
|
avalon_waitreq_in => avalon_waitrequest_in,
|
333 |
|
|
avalon_we_in => avalon_we,
|
334 |
|
|
avalon_addr_out => current_mem_addr_r(i),
|
335 |
|
|
avalon_we_out => avalon_wes(i),
|
336 |
|
|
avalon_be_out => current_be_r(i),
|
337 |
|
|
addr_match_out => matches(i),
|
338 |
|
|
addr_match_cmb_out => matches_cmb(i),
|
339 |
|
|
irq_out => irq_chan_r(i),
|
340 |
|
|
words_out => rx_words(i)
|
341 |
|
|
);
|
342 |
|
|
|
343 |
|
|
end generate packet_channels;
|
344 |
|
|
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
|
348 |
|
|
curr_chan_avalon_we_r <= or_reduce(avalon_wes and matches);
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
ava_temp : for i in 0 to total_channels_c-1 generate
|
352 |
|
|
j : for j in 0 to addr_width_g-1 generate
|
353 |
|
|
avalon_addr_temp(j)(i) <= current_mem_addr_r(i)(j);
|
354 |
|
|
end generate j;
|
355 |
|
|
|
356 |
|
|
k : for k in 0 to be_width_c-1 generate
|
357 |
|
|
avalon_be_temp(k)(i) <= current_be_r(i)(k);
|
358 |
|
|
end generate k;
|
359 |
|
|
end generate ava_temp;
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
avalon_address : for i in 0 to addr_width_g-1 generate
|
363 |
|
|
avalon_addr(i) <= or_reduce(avalon_addr_temp(i) and matches);
|
364 |
|
|
end generate avalon_address;
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
be : for i in 0 to be_width_c-1 generate
|
368 |
|
|
avalon_be(i) <= or_reduce(avalon_be_temp(i) and matches);
|
369 |
|
|
end generate be;
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
cpu_side : process (clk, rst_n)
|
373 |
|
|
variable legal_write : std_logic;
|
374 |
|
|
variable legal_read : std_logic;
|
375 |
|
|
variable n_chan : integer range total_channels_c-1 downto 0;
|
376 |
|
|
variable n_dest : integer range (2**conf_bits_c)-1 downto 0;
|
377 |
|
|
begin -- process cpu
|
378 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
379 |
|
|
for i in total_channels_c-1 downto 0 loop
|
380 |
|
|
mem_addr_r(i) <= (others => '0');
|
381 |
|
|
sender_addr_r(i) <= (others => '0');
|
382 |
|
|
irq_words_r(i) <= (others => '1');
|
383 |
|
|
end loop; -- i
|
384 |
|
|
avalon_cfg_readdata_out <= (others => '0');
|
385 |
|
|
init_chan_r <= (others => '0');
|
386 |
|
|
control_r <= (others => '0');
|
387 |
|
|
-- status for only rx signals..
|
388 |
|
|
status_r(1) <= '0';
|
389 |
|
|
tx_mem_addr_r <= (others => '0');
|
390 |
|
|
tx_comm_r <= (others => '0');
|
391 |
|
|
tx_words_r <= (others => '0');
|
392 |
|
|
rx_irq_out <= '0';
|
393 |
|
|
irq_reset_r <= '0';
|
394 |
|
|
unknown_rx_irq_r <= '0';
|
395 |
|
|
unknown_rx_r <= '0';
|
396 |
|
|
ignored_last_tx_r <= '0';
|
397 |
|
|
read_ack_r <= (others => '0');
|
398 |
|
|
|
399 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
400 |
|
|
|
401 |
|
|
read_ack_r <= (others => '0');
|
402 |
|
|
unknown_rx_r <= unknown_rx;
|
403 |
|
|
|
404 |
|
|
if unknown_rx = '1' and unknown_rx_r = '0' then
|
405 |
|
|
unknown_rx_irq_r <= '1';
|
406 |
|
|
end if;
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
-- set the IRQ. may be changed below if some IRQ
|
410 |
|
|
-- is cleared and others are pending.
|
411 |
|
|
if unknown_rx_irq_r = '1' or ignored_last_tx_r = '1' or
|
412 |
|
|
(irq_chan_r /= 0 and irq_reset_r = '0') then
|
413 |
|
|
-- irq ena bit...
|
414 |
|
|
rx_irq_out <= control_r(1);
|
415 |
|
|
end if;
|
416 |
|
|
|
417 |
|
|
irq_reset_r <= '0'; -- default
|
418 |
|
|
|
419 |
|
|
control_r(0) <= '0';
|
420 |
|
|
-- nullifies the tx start after CPU has set it
|
421 |
|
|
-- otherwise CPU can't keep up with HPD with small transfers
|
422 |
|
|
|
423 |
|
|
irq_ack_r <= (others => '0');
|
424 |
|
|
|
425 |
|
|
legal_write := avalon_cfg_cs_in and avalon_cfg_we_in;
|
426 |
|
|
legal_read := avalon_cfg_cs_in and avalon_cfg_re_in;
|
427 |
|
|
n_chan := conv_integer(avalon_cfg_addr_in(n_chans_bits_g+conf_bits_c-1 downto conf_bits_c));
|
428 |
|
|
n_dest := conv_integer(avalon_cfg_addr_in(conf_bits_c-1 downto 0));
|
429 |
|
|
|
430 |
|
|
if legal_write = '1' then
|
431 |
|
|
|
432 |
|
|
case n_dest is
|
433 |
|
|
|
434 |
|
|
when 0 => -- init channel
|
435 |
|
|
init_chan_r <= avalon_cfg_writedata_in(total_channels_c-1 downto 0);
|
436 |
|
|
|
437 |
|
|
when 1 => -- control
|
438 |
|
|
if ignore_tx_write = '0' then
|
439 |
|
|
control_r <= avalon_cfg_writedata_in(control_bits_c-1 downto 0);
|
440 |
|
|
end if;
|
441 |
|
|
|
442 |
|
|
-- remember wether a tx gets lost or not
|
443 |
|
|
if ignore_tx_write = '1' then
|
444 |
|
|
ignored_last_tx_r <= '1';
|
445 |
|
|
else
|
446 |
|
|
ignored_last_tx_r <= ignored_last_tx_r;
|
447 |
|
|
end if;
|
448 |
|
|
|
449 |
|
|
when 2 => -- irq status
|
450 |
|
|
|
451 |
|
|
-- goes down so that generates an edge
|
452 |
|
|
-- when many interrupts are pending.
|
453 |
|
|
rx_irq_out <= '0';
|
454 |
|
|
irq_reset_r <= '1';
|
455 |
|
|
|
456 |
|
|
irq_ack_r <= avalon_cfg_writedata_in(total_channels_c-1 downto 0);
|
457 |
|
|
|
458 |
|
|
if avalon_cfg_writedata_in(data_width_g-1) = '1' then
|
459 |
|
|
unknown_rx_irq_r <= '0';
|
460 |
|
|
end if;
|
461 |
|
|
|
462 |
|
|
if avalon_cfg_writedata_in(data_width_g-2) = '1' then
|
463 |
|
|
ignored_last_tx_r <= '0';
|
464 |
|
|
end if;
|
465 |
|
|
|
466 |
|
|
when 3 => -- tx mem addr
|
467 |
|
|
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then
|
468 |
|
|
tx_mem_addr_r <= avalon_cfg_writedata_in;
|
469 |
|
|
end if;
|
470 |
|
|
|
471 |
|
|
when 4 => -- tx words
|
472 |
|
|
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then
|
473 |
|
|
tx_words_r <= avalon_cfg_writedata_in(words_width_g-1 downto 0);
|
474 |
|
|
end if;
|
475 |
|
|
|
476 |
|
|
when 5 => -- tx command
|
477 |
|
|
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then
|
478 |
|
|
tx_comm_r <= avalon_cfg_writedata_in(4 downto 0);
|
479 |
|
|
end if;
|
480 |
|
|
|
481 |
|
|
when 6 => -- tx hibi addr
|
482 |
|
|
if avalon_cfg_waitrequest_out_s = '0' and ignore_tx_write = '0' then
|
483 |
|
|
tx_hibi_addr_r <= avalon_cfg_writedata_in;
|
484 |
|
|
end if;
|
485 |
|
|
|
486 |
|
|
when 8 => -- mem_addr
|
487 |
|
|
mem_addr_r(n_chan) <= avalon_cfg_writedata_in;
|
488 |
|
|
|
489 |
|
|
when 9 => -- irq_words
|
490 |
|
|
irq_words_r(n_chan) <=
|
491 |
|
|
avalon_cfg_writedata_in(words_width_g-1 downto 0);
|
492 |
|
|
-- if channel is streaming acknowledge the read
|
493 |
|
|
if (n_chan < n_stream_chans_g) then
|
494 |
|
|
read_ack_r(n_chan) <= '1';
|
495 |
|
|
end if;
|
496 |
|
|
|
497 |
|
|
when 10 => -- sender addr
|
498 |
|
|
sender_addr_r(n_chan) <= avalon_cfg_writedata_in;
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
when others =>
|
502 |
|
|
|
503 |
|
|
-- do nothing
|
504 |
|
|
|
505 |
|
|
end case;
|
506 |
|
|
end if;
|
507 |
|
|
|
508 |
|
|
|
509 |
|
|
if legal_read = '1' then
|
510 |
|
|
case n_dest is
|
511 |
|
|
|
512 |
|
|
when 0 => -- initialize
|
513 |
|
|
|
514 |
|
|
when 1 => -- control
|
515 |
|
|
avalon_cfg_readdata_out(15 downto control_bits_c) <=
|
516 |
|
|
(others => '0');
|
517 |
|
|
avalon_cfg_readdata_out(control_bits_c-1 downto 0) <= control_r;
|
518 |
|
|
avalon_cfg_readdata_out(31 downto status_bits_c+15) <=
|
519 |
|
|
(others => '0');
|
520 |
|
|
avalon_cfg_readdata_out(status_bits_c+15 downto 16) <= status_r;
|
521 |
|
|
|
522 |
|
|
when 2 => -- irq status
|
523 |
|
|
avalon_cfg_readdata_out(addr_width_g-1) <=
|
524 |
|
|
unknown_rx_irq_r;
|
525 |
|
|
avalon_cfg_readdata_out(addr_width_g-2) <=
|
526 |
|
|
ignored_last_tx_r;
|
527 |
|
|
avalon_cfg_readdata_out(total_channels_c-1 downto 0) <=
|
528 |
|
|
irq_chan_r;
|
529 |
|
|
avalon_cfg_readdata_out(addr_width_g-3 downto total_channels_c) <=
|
530 |
|
|
(others => '0');
|
531 |
|
|
|
532 |
|
|
when 7 =>
|
533 |
|
|
avalon_cfg_readdata_out(31 downto 0) <= hibi_data_in;
|
534 |
|
|
|
535 |
|
|
when 8 => -- rx mem addr
|
536 |
|
|
avalon_cfg_readdata_out <= mem_addr_r(n_chan);
|
537 |
|
|
|
538 |
|
|
when 9 => -- rx words
|
539 |
|
|
avalon_cfg_readdata_out(addr_width_g-1 downto words_width_g) <=
|
540 |
|
|
(others => '0');
|
541 |
|
|
avalon_cfg_readdata_out(words_width_g-1 downto 0) <=
|
542 |
|
|
irq_words_r(n_chan);
|
543 |
|
|
|
544 |
|
|
when 10 => -- rx hibi addr
|
545 |
|
|
avalon_cfg_readdata_out <= sender_addr_r(n_chan);
|
546 |
|
|
|
547 |
|
|
when others =>
|
548 |
|
|
-- do nothing;
|
549 |
|
|
end case;
|
550 |
|
|
end if;
|
551 |
|
|
|
552 |
|
|
|
553 |
|
|
if init_chan_r /= conv_std_logic_vector(0, total_channels_c) then
|
554 |
|
|
init_chan_r <= (others => '0');
|
555 |
|
|
end if;
|
556 |
|
|
|
557 |
|
|
end if;
|
558 |
|
|
end process cpu_side;
|
559 |
|
|
|
560 |
|
|
|
561 |
|
|
|
562 |
|
|
|
563 |
|
|
-- tx signals
|
564 |
|
|
-- done bit, start tx
|
565 |
|
|
status_r(0) <= tx_status_done_in;
|
566 |
|
|
tx_words_out <= tx_words_r;
|
567 |
|
|
tx_mem_addr_out <= tx_mem_addr_r;
|
568 |
|
|
tx_comm_out <= tx_comm_r;
|
569 |
|
|
tx_hibi_addr_out <= tx_hibi_addr_r;
|
570 |
|
|
|
571 |
|
|
tx_start : process (clk, rst_n)
|
572 |
|
|
|
573 |
|
|
begin -- process sel_tx_start
|
574 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
575 |
|
|
was_high_r <= '0';
|
576 |
|
|
tx_start_out <= '0';
|
577 |
|
|
|
578 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
579 |
|
|
if control_r(0) = '1' then
|
580 |
|
|
if was_high_r = '0' then
|
581 |
|
|
was_high_r <= '1';
|
582 |
|
|
tx_start_out <= '1';
|
583 |
|
|
else
|
584 |
|
|
was_high_r <= '1';
|
585 |
|
|
tx_start_out <= '0';
|
586 |
|
|
end if;
|
587 |
|
|
else
|
588 |
|
|
was_high_r <= '0';
|
589 |
|
|
tx_start_out <= '0';
|
590 |
|
|
end if;
|
591 |
|
|
end if;
|
592 |
|
|
end process tx_start;
|
593 |
|
|
|
594 |
|
|
end rtl;
|
595 |
|
|
|