OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sram/] [1.0/] [hdl/] [nios_ii_sram.qip] - Blame information for rev 147

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 147 lanttu
# clk_0
2
# cpu_0
3
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) cpu_0.sdc]
4
set_global_assignment -name SOURCE_FILE [file join $::quartus(qip_path) cpu_0.ocp]
5
# onchip_memory_0
6
# jtag_uart_0
7
# sram_0
8
set_global_assignment -name TCL_FILE C:/Users/lauri/ncit_summer_school/hw/altera_up_avalon_sram/Altera_UP_Avalon_SRAM_hw.tcl
9
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sram_0.v]
10
# timer_0
11
# hibi_pe_dma_0
12
#set_global_assignment -name TCL_FILE [file join $::quartus(qip_path) ip/hibi_pe_dma_hw.tcl]
13
 
14
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) hibi_pe_dma_0.vhd]
15
# sysid
16
# null
17
set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID 002170BA51F1000001380E6B5432
18
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.