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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sram/] [1.0/] [nios_ii_sram.1.0.xml] - Blame information for rev 188

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Line No. Rev Author Line
1 147 lanttu
2
3
4
5
6
7 
        Altera
8 
        ip.hwp.cpu
9 
        nios_ii_sram
10 
        1.0
11 188 lanttu 
        Nios2 subsystem using SRAM as a data and program memory.
12 
Includes HIBI_PE_DMA for hibi communication.
13 
 
14
15 147 lanttu
16
17 
                        clk
18
19
20
21 
                        false
22
23
24
25 
                                                CLK
26
27 
                                                        0
28 
                                                        0
29
30
31
32 
                                                clk_0
33
34 
                                                        0
35 
                                                        0
36
37
38
39
40 
                        8
41 
                        little
42
43
44 
                        hibi_master
45
46
47 157 lanttu
48
49
50 147 lanttu 
                        false
51
52
53
54 
                                                AV
55
56 
                                                        0
57 
                                                        0
58
59
60
61 
                                                hibi_av_out_from_the_hibi_pe_dma_0
62
63 
                                                        0
64 
                                                        0
65
66
67
68
69
70 
                                                COMM
71
72 
                                                        4
73 
                                                        0
74
75
76
77 
                                                hibi_comm_out_from_the_hibi_pe_dma_0
78
79 
                                                        4
80 
                                                        0
81
82
83
84
85
86 
                                                DATA
87
88 
                                                        31
89 
                                                        0
90
91
92
93 
                                                hibi_data_out_from_the_hibi_pe_dma_0
94
95 
                                                        31
96 
                                                        0
97
98
99
100
101
102 
                                                RE
103
104 
                                                        0
105 
                                                        0
106
107
108
109 
                                                hibi_re_out_from_the_hibi_pe_dma_0
110
111 
                                                        0
112 
                                                        0
113
114
115
116
117
118 
                                                WE
119
120 
                                                        0
121 
                                                        0
122
123
124
125 
                                                hibi_we_out_from_the_hibi_pe_dma_0
126
127 
                                                        0
128 
                                                        0
129
130
131
132
133 
                        8
134 
                        little
135
136
137 
                        rst_n
138
139
140
141 
                        false
142
143
144
145 
                                                RESETn
146
147 
                                                        0
148 
                                                        0
149
150
151
152 
                                                reset_n
153
154 
                                                        0
155 
                                                        0
156
157
158
159
160 
                        8
161 
                        little
162
163
164 
                        sram_if
165
166
167
168 
                        false
169
170
171
172 
                                                SRAM_UB_N_FROM_SRAM
173
174 
                                                        0
175 
                                                        0
176
177
178
179 
                                                SRAM_UB_N_from_the_sram_0
180
181 
                                                        0
182 
                                                        0
183
184
185
186
187
188 
                                                SRAM_WE_N_FROM_SRAM
189
190 
                                                        0
191 
                                                        0
192
193
194
195 
                                                SRAM_WE_N_from_the_sram_0
196
197 
                                                        0
198 
                                                        0
199
200
201
202
203
204 
                                                SRAM_LB_N_FROM_SRAM
205
206 
                                                        0
207 
                                                        0
208
209
210
211 
                                                SRAM_LB_N_from_the_sram_0
212
213 
                                                        0
214 
                                                        0
215
216
217
218
219
220 
                                                SRAM_CE_N_FROM_SRAM
221
222 
                                                        0
223 
                                                        0
224
225
226
227 
                                                SRAM_CE_N_from_the_sram_0
228
229 
                                                        0
230 
                                                        0
231
232
233
234
235
236 
                                                SRAM_OE_N_FROM_SRAM
237
238 
                                                        0
239 
                                                        0
240
241
242
243 
                                                SRAM_OE_N_from_the_sram_0
244
245 
                                                        0
246 
                                                        0
247
248
249
250
251
252 
                                                SRAM_DQ_TO_AND_FROM_SRAM
253
254 
                                                        15
255 
                                                        0
256
257
258
259 
                                                SRAM_DQ_to_and_from_the_sram_0
260
261 
                                                        15
262 
                                                        0
263
264
265
266
267
268 
                                                SRAM_ADDR_FROM_SRAM
269
270 
                                                        17
271 
                                                        0
272
273
274
275 
                                                SRAM_ADDR_from_the_sram_0
276
277 
                                                        17
278 
                                                        0
279
280
281
282
283 
                        8
284 
                        little
285
286
287 
                        hibi_slave
288
289
290 157 lanttu
291
292
293 147 lanttu 
                        false
294
295
296
297 
                                                AV
298
299 
                                                        0
300 
                                                        0
301
302
303
304 
                                                hibi_av_in_to_the_hibi_pe_dma_0
305
306 
                                                        0
307 
                                                        0
308
309
310
311
312
313 
                                                COMM
314
315 
                                                        4
316 
                                                        0
317
318
319
320 
                                                hibi_comm_in_to_the_hibi_pe_dma_0
321
322 
                                                        4
323 
                                                        0
324
325
326
327
328
329 
                                                DATA
330
331 
                                                        31
332 
                                                        0
333
334
335
336 
                                                hibi_data_in_to_the_hibi_pe_dma_0
337
338 
                                                        31
339 
                                                        0
340
341
342
343
344
345 
                                                EMPTY
346
347 
                                                        0
348 
                                                        0
349
350
351
352 
                                                hibi_empty_in_to_the_hibi_pe_dma_0
353
354 
                                                        0
355 
                                                        0
356
357
358
359
360
361 
                                                FULL
362
363 
                                                        0
364 
                                                        0
365
366
367
368 
                                                hibi_full_in_to_the_hibi_pe_dma_0
369
370 
                                                        0
371 
                                                        0
372
373
374
375
376 
                        8
377 
                        little
378
379
380
381
382 157 lanttu 
                        avalon_addr_space
383 
                        Avalon address space. (local)
384 
                        4G
385 147 lanttu 
                        32
386 157 lanttu
387
388 
                                        .bss
389 
                                        0x00800000
390 
                                        512
391
392
393 
                                        .entry
394 
                                        0x00800400
395 
                                        512
396
397
398 
                                        .exceptions
399 
                                        0x00800200
400 
                                        512
401
402
403 
                                        .heap
404 
                                        0x00800800
405 
                                        512
406
407
408 
                                        .rodata
409 
                                        0x00800E00
410 
                                        512
411
412
413 
                                        .rwdata
414 
                                        0x00800A00
415 
                                        512
416
417
418 
                                        .stack
419 
                                        0x00800600
420 
                                        512
421
422
423 
                                        .text
424 
                                        0x00800C00
425 
                                        512
426
427
428 
                                        Shared_memory
429 
                                        0x1000000
430 
                                        4K
431
432
433 188 lanttu 
                        32
434 157 lanttu
435 
                                avalon_addr_space
436
437 
                                        HIBI_PE_DMA
438 188 lanttu 
                                        0x500
439 
                                        64
440 157 lanttu 
                                        32
441 188 lanttu 
                                        register
442
443 
                                                RX_INITIALIZE
444 
                                                Initializes the channel
445 
                                                0
446 
                                                0x0
447 
                                                32
448 
                                                false
449 
                                                write-only
450
451
452 
                                                CONTROL
453 
                                                Control register
454 
                                                0
455 
                                                0x1
456 
                                                32
457 
                                                read-write
458
459
460 
                                                IRQ_STATUS
461 
                                                Read IRQ status and acknoledge interrupts
462 
                                                0
463 
                                                0x2
464 
                                                32
465 
                                                read-write
466
467
468 
                                                TX_MEM_ADDR
469 
                                                Address where data to be sent begins
470 
                                                0
471 
                                                0x3
472 
                                                32
473 
                                                write-only
474
475
476 
                                                TX_WORDS
477 
                                                How many words to send
478 
                                                0
479 
                                                0x4
480 
                                                32
481 
                                                read-only
482
483
484 
                                                TX_COMM
485 
                                                Hibi command to send the data with
486 
                                                0
487 
                                                0x5
488 
                                                32
489 
                                                write-only
490
491
492 
                                                TX_HIBI_ADDR
493 
                                                Hibi address to send the data
494 
                                                0
495 
                                                0x6
496 
                                                32
497 
                                                write-only
498
499
500 
                                                RX_HIBI_DATA
501 
                                                Current data on hibi rx interface
502 
                                                0
503 
                                                0x7
504 
                                                32
505 
                                                read-only
506
507
508 
                                                RX_MEM_ADDR
509 
                                                Address where channel n stores received data
510 
                                                0
511 
                                                0x8
512 
                                                32
513 
                                                read-write
514
515
516 
                                                RX_WORDS
517 
                                                How many words to receive for packet channel n or read
518 
acknowledge for stream channel n
519 
                                                0
520 
                                                0x9
521 
                                                32
522 
                                                read-write
523
524
525 
                                                RX_HIBI_ADDR
526 
                                                Hibi address for channel n to listen
527 
                                                0
528 
                                                0xA
529 
                                                32
530 
                                                read-write
531
532 157 lanttu
533
534 
                                        JTAG_UART
535 188 lanttu 
                                        0x100
536 157 lanttu 
                                        4
537 
                                        32
538 
                                        reserved
539
540
541 
                                        TIMER
542 188 lanttu 
                                        0x300
543 157 lanttu 
                                        4
544 
                                        32
545 
                                        reserved
546
547
548 
                                        SRAM
549 
                                        0x00800000
550 
                                        8M
551 
                                        32
552 
                                        memory
553
554
555 
                                        SYSID
556 188 lanttu 
                                        0x200
557 157 lanttu 
                                        4
558 
                                        32
559 
                                        reserved
560
561
562 
                                        ONCHIP_MEM
563 
                                        0x1000000
564 
                                        4K
565 
                                        32
566 
                                        memory
567
568
569 147 lanttu
570 157 lanttu
571 
                        hibi_addr_space
572 
                        HIBI address space
573 
                        4G
574 
                        32
575 
                        8
576
577 147 lanttu
578 157 lanttu
579
580 
                        hibi_mem_map
581 188 lanttu
582 
                                hibi_addr_block
583 
                                0x0
584 
                                32
585 
                                32
586 
                                reserved
587
588 157 lanttu 
                        32
589
590
591 147 lanttu
592
593
594 
                                rtl
595 
                                VHDL:Quartus:
596 
                                nios_ii_sram
597
598 
                                        hdlSources
599
600
601
602
603
604 
                                SRAM_ADDR_from_the_sram_0
605
606 
                                        out
607
608 
                                                17
609 
                                                0
610
611
612
613
614
615 
                                SRAM_CE_N_from_the_sram_0
616
617 
                                        out
618
619
620
621
622 
                                SRAM_DQ_to_and_from_the_sram_0
623
624 
                                        inout
625
626 
                                                15
627 
                                                0
628
629
630
631
632
633 
                                SRAM_LB_N_from_the_sram_0
634
635 
                                        out
636
637
638
639
640 
                                SRAM_OE_N_from_the_sram_0
641
642 
                                        out
643
644
645
646
647 
                                SRAM_UB_N_from_the_sram_0
648
649 
                                        out
650
651
652
653
654 
                                SRAM_WE_N_from_the_sram_0
655
656 
                                        out
657
658
659
660
661 
                                clk_0
662
663 
                                        in
664
665 
                                                0
666 
                                                0
667
668
669
670
671
672 
                                hibi_av_in_to_the_hibi_pe_dma_0
673
674 
                                        in
675
676 
                                                0
677 
                                                0
678
679
680
681
682
683 
                                hibi_av_out_from_the_hibi_pe_dma_0
684
685 
                                        out
686
687
688
689
690 
                                hibi_comm_in_to_the_hibi_pe_dma_0
691
692 
                                        in
693
694 
                                                4
695 
                                                0
696
697
698
699
700
701 
                                hibi_comm_out_from_the_hibi_pe_dma_0
702
703 
                                        out
704
705 
                                                4
706 
                                                0
707
708
709
710
711
712 
                                hibi_data_in_to_the_hibi_pe_dma_0
713
714 
                                        in
715
716 
                                                31
717 
                                                0
718
719
720
721
722
723 
                                hibi_data_out_from_the_hibi_pe_dma_0
724
725 
                                        out
726
727 
                                                31
728 
                                                0
729
730
731
732
733
734 
                                hibi_empty_in_to_the_hibi_pe_dma_0
735
736 
                                        in
737
738
739
740
741 
                                hibi_full_in_to_the_hibi_pe_dma_0
742
743 
                                        in
744
745
746
747
748 
                                hibi_re_out_from_the_hibi_pe_dma_0
749
750 
                                        out
751
752
753
754
755 
                                hibi_we_out_from_the_hibi_pe_dma_0
756
757 
                                        out
758
759
760
761
762 
                                reset_n
763
764 
                                        in
765
766
767
768
769
770
771
772 
                        hdlSources
773
774 
                                hdl/timer_0.v
775 
                                verilogSource
776 
                                false
777
778
779 
                                hdl/cpu_0.v
780 
                                verilogSource
781 
                                false
782
783
784 
                                hdl/cpu_0_jtag_debug_module_sysclk.v
785 
                                verilogSource
786 
                                false
787
788
789 
                                hdl/cpu_0_jtag_debug_module_tck.v
790 
                                verilogSource
791 
                                false
792
793
794 
                                hdl/cpu_0_jtag_debug_module_wrapper.v
795 
                                verilogSource
796 
                                false
797
798
799 
                                hdl/cpu_0_mult_cell.v
800 
                                verilogSource
801 
                                false
802
803
804 
                                hdl/cpu_0_oci_test_bench.v
805 
                                verilogSource
806 
                                false
807
808
809 
                                hdl/cpu_0_test_bench.v
810 
                                verilogSource
811 
                                false
812
813
814 
                                hdl/jtag_uart_0.v
815 
                                verilogSource
816 
                                false
817
818
819 
                                hdl/nios_ii_sram.v
820 
                                verilogSource
821 
                                false
822
823
824 
                                hdl/sram_0.v
825 
                                verilogSource
826 
                                false
827
828
829 
                                hdl/nios_ii_sram.qip
830 
                                quartusIPFile
831 
                                false
832
833
834 
                                hdl/sysid.v
835 
                                verilogSource
836 
                                false
837
838
839 
                                hdl/ip/hpd_rx_stream.vhd
840 
                                vhdlSource
841 
                                false
842
843
844 
                                hdl/ip/hpd_tx_control.vhd
845 
                                vhdlSource
846 
                                false
847
848
849 
                                hdl/ip/hibi_pe_dma.vhd
850 
                                vhdlSource
851 
                                false
852
853
854 
                                hdl/ip/hibi_pe_dma_hw.tcl
855 
                                tclScript
856 
                                false
857
858
859 
                                hdl/ip/hibi_pe_dma_sw.tcl
860 
                                tclScript
861 
                                false
862
863
864 
                                hdl/ip/hpd_rx_and_conf.vhd
865 
                                vhdlSource
866 
                                false
867
868
869 
                                hdl/ip/hpd_rx_packet.vhd
870 
                                vhdlSource
871 
                                false
872
873
874 
                                hdl/onchip_memory_0.v
875 
                                verilogSource
876 
                                false
877
878
879 188 lanttu
880 
                        avalon_addr_space_header
881 
                        Contains header files generated for the component.
882 
                        generatedFiles
883
884 
                                headers/avalon_addr_space.h
885 
                                cSource
886 
                                cppSource
887 
                                true
888 
                                A header file generated by Kactus2.
889 
This file contains the register and memory addresses defined in the memory map(s)
890
891
892 147 lanttu
893
894
895 
                        nios2
896 157 lanttu
897 147 lanttu
898
899
900
901
902 
                                IP
903 
                                HW
904 
                                Fixed
905
906
907
908 
                                        software
909
910
911
912
913
914

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