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# +----------------------------------------------------------------------------+
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# | License Agreement |
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# | Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. |
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# | All rights reserved. |
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# | Any megafunction design, and related net list (encrypted or decrypted), |
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# | support information, device programming or simulation file, and any other |
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# | associated documentation or information provided by Altera or a partner |
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# | under Altera's Megafunction Partnership Program may be used only to |
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# | program PLD devices (but not masked PLD devices) from Altera. Any other |
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# | use of such megafunction design, net list, support information, device |
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# | programming or simulation file, or any other related documentation or |
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# | information is prohibited for any other purpose, including, but not |
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# | limited to modification, reverse engineering, de-compiling, or use with |
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# | any other silicon devices, unless such use is explicitly licensed under |
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# | a separate agreement with Altera or a megafunction partner. Title to |
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# | the intellectual property, including patents, copyrights, trademarks, |
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# | trade secrets, or maskworks, embodied in any such megafunction design, |
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# | net list, support information, device programming or simulation file, or |
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# | any other related documentation or information provided by Altera or a |
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# | megafunction partner, remains with Altera, the megafunction partner, or |
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# | their respective licensors. No other licenses, including any licenses |
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# | needed under any third party's intellectual property, are provided herein.|
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# | Copying or modifying any file, or portion thereof, to which this notice |
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# | is attached violates this copyright. |
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# | |
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# | THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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# | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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# | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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# | THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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# | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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# | FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS |
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# | IN THIS FILE. |
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# | This agreement shall be governed in all respects by the laws of the State |
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# | of California and by the laws of the United States of America. |
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# +----------------------------------------------------------------------------+
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# TCL File Generated by Altera University Program
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# DO NOT MODIFY
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# +-----------------------------------
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# | module altera_up_avalon_sram
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set_module_property DESCRIPTION "SRAM/SSRAM Controller for DE Boards"
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set_module_property NAME altera_up_avalon_sram
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set_module_property VERSION 9.0
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set_module_property GROUP "University Program/Memory"
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set_module_property AUTHOR "Altera University Program"
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set_module_property DISPLAY_NAME "SRAM/SSRAM Controller"
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set_module_property DATASHEET_URL "ftp.altera.com/up/archive/QII_9.0/Altera_Material/University_Program_IP/Memory/SRAM_Controller.pdf"
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#set_module_property TOP_LEVEL_HDL_FILE Altera_UP_Avalon_SRAM.v
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE false
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set_module_property SIMULATION_MODEL_IN_VERILOG false
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set_module_property SIMULATION_MODEL_IN_VHDL false
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set_module_property SIMULATION_MODEL_HAS_TULIPS false
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set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
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set_module_property ELABORATION_CALLBACK elaborate
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set_module_property GENERATION_CALLBACK generate
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | files
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#add_file Altera_UP_Avalon_SRAM.v {SYNTHESIS SIMULATION}
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# +-----------------------------------
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# +-----------------------------------
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# | parameters
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add_parameter board string DE2
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set_parameter_property board DISPLAY_NAME "DE Board"
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set_parameter_property board GROUP "Configurations"
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set_parameter_property board UNITS None
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set_parameter_property board AFFECTS_PORT_WIDTHS true
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set_parameter_property board ALLOWED_RANGES {DE1 DE2 "DE2-70"}
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set_parameter_property board VISIBLE true
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set_parameter_property board ENABLED true
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add_parameter pixel_buffer boolean false
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set_parameter_property pixel_buffer DISPLAY_NAME "Use as a pixel buffer for video out"
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set_parameter_property pixel_buffer GROUP "Configurations"
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set_parameter_property pixel_buffer UNITS None
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set_parameter_property pixel_buffer AFFECTS_PORT_WIDTHS true
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set_parameter_property pixel_buffer VISIBLE true
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set_parameter_property pixel_buffer ENABLED true
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# +-----------------------------------
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# +-----------------------------------
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# | connection point clock_reset
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add_interface clock_reset clock end
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set_interface_property clock_reset ptfSchematicName ""
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add_interface_port clock_reset clk clk Input 1
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add_interface_port clock_reset reset reset Input 1
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# +-----------------------------------
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# +-----------------------------------
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# | connection point external_interface
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add_interface external_interface conduit end
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set_interface_property external_interface ASSOCIATED_CLOCK clock_reset
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | Elaboration function
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proc elaborate {} {
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set board [ get_parameter_value "board" ]
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set pixel_buffer [ get_parameter_value "pixel_buffer" ]
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if { $board == "DE2-70" } {
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# +-----------------------------------
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# | connection point avalon_ssram_slave
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# |
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add_interface avalon_ssram_slave avalon end
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set_interface_property avalon_ssram_slave holdTime 0
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set_interface_property avalon_ssram_slave linewrapBursts false
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set_interface_property avalon_ssram_slave minimumUninterruptedRunLength 1
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set_interface_property avalon_ssram_slave bridgesToMaster ""
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if { $pixel_buffer } {
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set_interface_property avalon_ssram_slave isMemoryDevice false
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} else {
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set_interface_property avalon_ssram_slave isMemoryDevice true
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}
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set_interface_property avalon_ssram_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_ssram_slave addressSpan 2097152
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set_interface_property avalon_ssram_slave timingUnits Cycles
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set_interface_property avalon_ssram_slave setupTime 0
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set_interface_property avalon_ssram_slave writeWaitTime 1
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set_interface_property avalon_ssram_slave writeWaitStates 1
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set_interface_property avalon_ssram_slave isNonVolatileStorage false
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set_interface_property avalon_ssram_slave addressAlignment DYNAMIC
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set_interface_property avalon_ssram_slave maximumPendingReadTransactions 0
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set_interface_property avalon_ssram_slave readWaitTime 2
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set_interface_property avalon_ssram_slave readLatency 0
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set_interface_property avalon_ssram_slave printableDevice false
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set_interface_property avalon_ssram_slave ASSOCIATED_CLOCK clock_reset
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add_interface_port avalon_ssram_slave address address Input 19
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add_interface_port avalon_ssram_slave byteenable byteenable Input 4
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add_interface_port avalon_ssram_slave read read Input 1
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add_interface_port avalon_ssram_slave write write Input 1
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add_interface_port avalon_ssram_slave writedata writedata Input 32
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add_interface_port avalon_ssram_slave readdata readdata Output 32
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# |
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# +-----------------------------------
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# Add signals to the connection point external_interface
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add_interface_port external_interface SRAM_DQ export Bidir 32
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add_interface_port external_interface SRAM_DPA export Bidir 4
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add_interface_port external_interface SRAM_ADDR export Output 19
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add_interface_port external_interface SRAM_ADSC_N export Output 1
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add_interface_port external_interface SRAM_ADSP_N export Output 1
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add_interface_port external_interface SRAM_ADV_N export Output 1
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add_interface_port external_interface SRAM_BE_N export Output 4
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add_interface_port external_interface SRAM_CE1_N export Output 1
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add_interface_port external_interface SRAM_CE2 export Output 1
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add_interface_port external_interface SRAM_CE3_N export Output 1
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add_interface_port external_interface SRAM_GW_N export Output 1
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add_interface_port external_interface SRAM_OE_N export Output 1
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add_interface_port external_interface SRAM_WE_N export Output 1
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add_interface_port external_interface SRAM_CLK export Output 1
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} else {
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# +-----------------------------------
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# | connection point avalon_sram_slave
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# |
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add_interface avalon_sram_slave avalon end
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set_interface_property avalon_sram_slave holdTime 0
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set_interface_property avalon_sram_slave linewrapBursts false
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set_interface_property avalon_sram_slave minimumUninterruptedRunLength 1
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set_interface_property avalon_sram_slave bridgesToMaster ""
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if { $pixel_buffer } {
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set_interface_property avalon_sram_slave isMemoryDevice false
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} else {
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set_interface_property avalon_sram_slave isMemoryDevice true
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}
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set_interface_property avalon_sram_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_sram_slave addressSpan 524288
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set_interface_property avalon_sram_slave timingUnits Cycles
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set_interface_property avalon_sram_slave setupTime 0
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set_interface_property avalon_sram_slave writeWaitTime 0
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set_interface_property avalon_sram_slave isNonVolatileStorage false
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set_interface_property avalon_sram_slave addressAlignment DYNAMIC
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set_interface_property avalon_sram_slave readWaitStates 0
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set_interface_property avalon_sram_slave maximumPendingReadTransactions 0
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set_interface_property avalon_sram_slave readWaitTime 0
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set_interface_property avalon_sram_slave readLatency 2
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set_interface_property avalon_sram_slave printableDevice false
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set_interface_property avalon_sram_slave ASSOCIATED_CLOCK clock_reset
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add_interface_port avalon_sram_slave address address Input 18
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add_interface_port avalon_sram_slave byteenable byteenable Input 2
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add_interface_port avalon_sram_slave read read Input 1
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add_interface_port avalon_sram_slave write write Input 1
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add_interface_port avalon_sram_slave writedata writedata Input 16
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add_interface_port avalon_sram_slave readdata readdata Output 16
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# |
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# +-----------------------------------
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# Add signals to the connection point external_interface
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add_interface_port external_interface SRAM_DQ export Bidir 16
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add_interface_port external_interface SRAM_ADDR export Output 18
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add_interface_port external_interface SRAM_LB_N export Output 1
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add_interface_port external_interface SRAM_UB_N export Output 1
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add_interface_port external_interface SRAM_CE_N export Output 1
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add_interface_port external_interface SRAM_OE_N export Output 1
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add_interface_port external_interface SRAM_WE_N export Output 1
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}
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}
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | Generation function
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proc generate {} {
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send_message info "Starting Generation of SRAM or SSRAM Controller"
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# get generation settings
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set language [ format "lang=%s" [ get_generation_setting HDL_LANGUAGE ] ]
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set outdir [ format "dir=%s" [ get_generation_setting OUTPUT_DIRECTORY ] ]
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set outname [ format "name=%s" [ get_generation_setting OUTPUT_NAME ] ]
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# get parameter values
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set board [ get_parameter_value "board" ]
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# set section value
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# set top_level_ports and external_port
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set top_level_name [ format "top_level_name=%s" [ get_project_property QUARTUS_PROJECT_NAME ] ]
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set top_level_ports "top_level_ports="
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set module_ports "module_ports="
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foreach port [ get_interface_ports external_interface ] {
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set direction [ get_port_property $port DIRECTION ]
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set width [ get_port_property $port WIDTH ]
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set top_level_ports "$top_level_ports$port:$direction:$width;"
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set module_ports "$module_ports$port:$direction:$width:$port;"
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}
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# set arguments
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if { $board == "DE2-70" } {
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set files "files=Altera_UP_Avalon_SSRAM.v"
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} else {
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set files "files=Altera_UP_Avalon_SRAM.v"
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}
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set params ""
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set sections ""
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# get generation settings
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# set dest_language [ get_generation_setting HDL_LANGUAGE ]
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set dest_dir [ get_generation_setting OUTPUT_DIRECTORY ]
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set dest_name [ get_generation_setting OUTPUT_NAME ]
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add_file "$dest_dir$dest_name.v" {SYNTHESIS SIMULATION}
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# Generate HDL
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source "UP_IP_Generator.tcl"
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if { $board == "DE2-70" } {
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up_generate "$dest_dir$dest_name.v" "hdl/Altera_UP_Avalon_SSRAM.v" $dest_name $params $sections
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} else {
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up_generate "$dest_dir$dest_name.v" "hdl/Altera_UP_Avalon_SRAM.v" $dest_name $params $sections
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}
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}
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# |
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# +-----------------------------------
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