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[/] [funbase_ip_library/] [trunk/] [TUT/] [board/] [altera_de2_board/] [1.0/] [altera_de2_board.design.1.0.xml] - Blame information for rev 145

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        TUT
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        board
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        altera_de2_board.design
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        1.0
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                        dm_9000_eth_ctrl
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                        clock_osc_50MHz
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                        push_buttons_0
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                        SDRAM_8MB
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                        SRAM_512KB
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                        cyclone_II_0
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                        push_buttons_0_button_17_to_cyclone_II_0_rst_n
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                        cyclone_II_0_DM9000A_to_dm_9000_eth_ctrl_eth_fpga
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                        clock_oscillator_0_clk_out_to_cyclone_II_0_clk_in
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                        cyclone_II_0_sram_if_to_unnamed_1_sram_if
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                        cyclone_II_0_sdram_clk_to_SDRAM_8MB_sdram_clk
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                        cyclone_II_0_sdram_if_to_SDRAM_8MB_sdram_if
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