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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dct_to_hibi/] [1.0/] [tb/] [tb_pinger.vhd] - Blame information for rev 145

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1 145 lanttu 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_pinger is
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  generic (
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    data_width_g     : integer := 32;
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    comm_width_g     : integer := 3;
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    own_hibi_addr_g  : integer;
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    init_send_addr_g : integer;
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    start_sending_g  : integer );
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  port (
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    clk      : in  std_logic;
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    rst_n    : in  std_logic;
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    data_in  : in  std_logic_vector(data_width_g-1 downto 0);
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    comm_in  : in  std_logic_vector(comm_width_g-1 downto 0);
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    av_in    : in  std_logic;
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    empty_in : in  std_logic;
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    re_out   : out std_logic;
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    data_out : out std_logic_vector(data_width_g-1 downto 0);
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    comm_out : out std_logic_vector(comm_width_g-1 downto 0);
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    av_out   : out std_logic;
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    full_in  : in  std_logic;
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    we_out   : out std_logic);
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end tb_pinger;
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architecture rtl of tb_pinger is
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  signal data_counter_r : integer;
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signal inc_data_counter : std_logic;
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  signal wait_delay_r    : integer;
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  signal delay_counter_r : integer;
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  signal ping_counter_r  : integer;
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  type   states is (wait_data, wait_counter, send_av, send_amount, send_data);
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  signal state           : states;
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  signal ret_addr_r      : std_logic_vector(data_width_g-1 downto 0);
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  signal amount_r : std_logic_vector(data_width_g-1 downto 0);
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  signal addr_sent : std_logic;
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  signal data_sent : std_logic;
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  signal amount_sent : std_logic;
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begin  -- rtl
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  process (clk, rst_n)
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  begin  -- process
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    if rst_n = '0' then                 -- asynchronous reset (active low)
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      ret_addr_r      <= std_logic_vector(to_unsigned(init_send_addr_g, data_width_g));
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      if start_sending_g = 1 then
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        state           <= send_av;
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      else
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        state <= wait_data;
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      end if;
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      wait_delay_r    <= 1;
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      ping_counter_r  <= 0;
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      delay_counter_r <= 0;
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      data_counter_r  <= 0;
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      amount_r <= std_logic_vector( to_unsigned( 10, data_width_g) );
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    elsif clk'event and clk = '1' then  -- rising clock edge
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      case state is
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        when wait_data =>
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          if av_in = '0' and empty_in = '0' then
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            if data_counter_r = 0 then
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              amount_r <= data_in;
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            end if;
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            if data_counter_r = 1 then
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              ret_addr_r <= data_in;
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            end if;
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            if data_counter_r = to_integer(unsigned(amount_r)+1) then
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              state          <= wait_counter;
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              data_counter_r <= 0;
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            else
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              data_counter_r <= data_counter_r + 1;
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            end if;
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          end if;
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        when wait_counter =>
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          if delay_counter_r = wait_delay_r then
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            state           <= send_av;
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            delay_counter_r <= 0;
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          else
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            delay_counter_r <= delay_counter_r + 1;
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          end if;
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        when send_av =>
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          if addr_sent = '1' then
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            state <= send_amount;
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          end if;
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        when send_amount =>
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          if amount_sent = '1' then
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            state <= send_data;
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          end if;
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        when send_data =>
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          if inc_data_counter = '1' then
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            data_counter_r <= data_counter_r + 1;
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          end if;
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          if data_sent = '1' then
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            state          <= wait_data;
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            data_counter_r <= 0;
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            if ping_counter_r = 100 then
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              ping_counter_r <= 0;
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              wait_delay_r   <= wait_delay_r + 1;
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            else
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              ping_counter_r <= ping_counter_r + 1;
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            end if;
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          end if;
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      end case;
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    end if;
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  end process;
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  process (full_in, state, ret_addr_r, rst_n, data_counter_r, amount_r)
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  begin  -- process
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    av_out    <= '0';
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    we_out    <= '0';
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    data_out  <= (others => '0');
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    comm_out  <= (others => '0');
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    re_out    <= '0';
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    data_sent <= '0';
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    addr_sent <= '0';
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    amount_sent <= '0';
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    inc_data_counter <= '0';
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    case state is
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      when wait_data =>
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        re_out <= '1';
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      when wait_counter =>
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        re_out <= '1';
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      when send_av =>
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        if full_in = '0' and rst_n = '1' then
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          we_out    <= '1';
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          av_out    <= '1';
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          data_out  <= ret_addr_r;
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          comm_out  <= "010";
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          addr_sent <= '1';
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        end if;
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      when send_amount =>
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        if full_in = '0' then
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          we_out    <= '1';
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          data_out  <= std_logic_vector( unsigned( amount_r ) + 1 );
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          comm_out  <= "010";
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          amount_sent <= '1';
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        end if;
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      when send_data =>
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        if full_in = '0' then
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          we_out   <= '1';
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          if data_counter_r = 0 then
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            data_out <= std_logic_vector(to_unsigned(own_hibi_addr_g, data_width_g));
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          else
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            data_out <= std_logic_vector(to_unsigned(data_counter_r,data_width_g));
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          end if;
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          comm_out <= "010";
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          inc_data_counter <= '1';
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          if data_counter_r = to_integer( unsigned(amount_r) + 1) then
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            data_sent <= '1';
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          end if;
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176 
        end if;
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    end case;
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  end process;
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end rtl;

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