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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [common_da/] [Serial_adder.vhd] - Blame information for rev 145

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------------------------------------------------------------------------------
-- Author               : Timo Alho
-- e-mail               : timo.a.alho@tut.fi
-- Date                 : 14.06.2004 14:08:22
-- File                 : Serial_adder.vhd
-- Design               : 
------------------------------------------------------------------------------
-- Description  : Serial adder. Consist of one full adder and register for
-- carrybit.
------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
 
ENTITY Serial_adder IS
   PORT(
      clk     : IN     std_logic;
      in0     : IN     std_logic;   --serial data input 0
      in1     : IN     std_logic;   --serial data input 1
      rst_n   : IN     std_logic;
      start   : IN     std_logic;   --start (ignores carrybit)
      sum_out : OUT    std_logic    --serial data outuput
   );
 
-- Declarations
 
END Serial_adder ;
 
--
ARCHITECTURE rtl OF Serial_adder IS
 
  SIGNAL carry_bit_r : std_logic;       --register, where carry bit is stored
  SIGNAL carry_bit   : std_logic;       --internal signal for carry bit
  SIGNAL sum         : std_logic;       --internal signal for sum
BEGIN
 
  clocked : PROCESS (clk, rst_n)
  BEGIN  -- PROCESS clocked
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
      carry_bit_r <= '0';
 
    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
      carry_bit_r <= carry_bit;
    END IF;
  END PROCESS clocked;
 
  calc : PROCESS (start, carry_bit_r, in0, in1)
 
    VARIABLE temp1 : std_logic_vector(1 DOWNTO 0);
    VARIABLE temp2 : std_logic_vector(2 DOWNTO 0);
 
  BEGIN  -- PROCESS calc
    IF (start = '1') THEN
      temp1 := in0 & in1;
      CASE temp1 IS
        WHEN "00"   =>
          sum       <= '0';
          carry_bit <= '0';
        WHEN "01"   =>
          sum       <= '1';
          carry_bit <= '0';
        WHEN "10"   =>
          sum       <= '1';
          carry_bit <= '0';
        WHEN OTHERS =>
          sum       <= '0';
          carry_bit <= '1';
      END CASE;
 
    ELSE
      temp2 := carry_bit_r & in0 & in1;
      CASE temp2 IS
        WHEN "000"  =>
          sum       <= '0';
          carry_bit <= '0';
        WHEN "001"  =>
          sum       <= '1';
          carry_bit <= '0';
        WHEN "010"  =>
          sum       <= '1';
          carry_bit <= '0';
        WHEN "011"  =>
          sum       <= '0';
          carry_bit <= '1';
        WHEN "100"  =>
          sum       <= '1';
          carry_bit <= '0';
        WHEN "101"  =>
          sum       <= '0';
          carry_bit <= '1';
        WHEN "110"  =>
          sum       <= '0';
          carry_bit <= '1';
        WHEN OTHERS =>
          sum       <= '1';
          carry_bit <= '1';
      END CASE;
    END IF;
 
  END PROCESS calc;
 
  sum_out <= sum;
 
 
END rtl;
 

Line No.	Rev	Author	Line
1	145	lanttu	`------------------------------------------------------------------------------`
2			`-- Author : Timo Alho`
3			`-- e-mail : timo.a.alho@tut.fi`
4			`-- Date : 14.06.2004 14:08:22`
5			`-- File : Serial_adder.vhd`
6			`-- Design :`
7			`------------------------------------------------------------------------------`
8			`-- Description : Serial adder. Consist of one full adder and register for`
9			`-- carrybit.`
10			`------------------------------------------------------------------------------`
11			`LIBRARY ieee;`
12			`USE ieee.std_logic_1164.ALL;`
13			`USE ieee.std_logic_arith.ALL;`
14
15			`ENTITY Serial_adder IS`
16			`PORT(`
17			`clk : IN std_logic;`
18			`in0 : IN std_logic; --serial data input 0`
19			`in1 : IN std_logic; --serial data input 1`
20			`rst_n : IN std_logic;`
21			`start : IN std_logic; --start (ignores carrybit)`
22			`sum_out : OUT std_logic --serial data outuput`
23			`);`
24
25			`-- Declarations`
26
27			`END Serial_adder ;`
28
29			`--`
30			`ARCHITECTURE rtl OF Serial_adder IS`
31
32			`SIGNAL carry_bit_r : std_logic; --register, where carry bit is stored`
33			`SIGNAL carry_bit : std_logic; --internal signal for carry bit`
34			`SIGNAL sum : std_logic; --internal signal for sum`
35			`BEGIN`
36
37			`clocked : PROCESS (clk, rst_n)`
38			`BEGIN -- PROCESS clocked`
39			`IF rst_n = '0' THEN -- asynchronous reset (active low)`
40			`carry_bit_r <= '0';`
41
42			`ELSIF clk'event AND clk = '1' THEN -- rising clock edge`
43			`carry_bit_r <= carry_bit;`
44			`END IF;`
45			`END PROCESS clocked;`
46
47			`calc : PROCESS (start, carry_bit_r, in0, in1)`
48
49			`VARIABLE temp1 : std_logic_vector(1 DOWNTO 0);`
50			`VARIABLE temp2 : std_logic_vector(2 DOWNTO 0);`
51
52			`BEGIN -- PROCESS calc`
53			`IF (start = '1') THEN`
54			`temp1 := in0 & in1;`
55			`CASE temp1 IS`
56			`WHEN "00" =>`
57			`sum <= '0';`
58			`carry_bit <= '0';`
59			`WHEN "01" =>`
60			`sum <= '1';`
61			`carry_bit <= '0';`
62			`WHEN "10" =>`
63			`sum <= '1';`
64			`carry_bit <= '0';`
65			`WHEN OTHERS =>`
66			`sum <= '0';`
67			`carry_bit <= '1';`
68			`END CASE;`
69
70			`ELSE`
71			`temp2 := carry_bit_r & in0 & in1;`
72			`CASE temp2 IS`
73			`WHEN "000" =>`
74			`sum <= '0';`
75			`carry_bit <= '0';`
76			`WHEN "001" =>`
77			`sum <= '1';`
78			`carry_bit <= '0';`
79			`WHEN "010" =>`
80			`sum <= '1';`
81			`carry_bit <= '0';`
82			`WHEN "011" =>`
83			`sum <= '0';`
84			`carry_bit <= '1';`
85			`WHEN "100" =>`
86			`sum <= '1';`
87			`carry_bit <= '0';`
88			`WHEN "101" =>`
89			`sum <= '0';`
90			`carry_bit <= '1';`
91			`WHEN "110" =>`
92			`sum <= '0';`
93			`carry_bit <= '1';`
94			`WHEN OTHERS =>`
95			`sum <= '1';`
96			`carry_bit <= '1';`
97			`END CASE;`
98			`END IF;`
99
100			`END PROCESS calc;`
101
102			`sum_out <= sum;`
103
104
105			`END rtl;`
106

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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [common_da/] [Serial_adder.vhd] - Blame information for rev 145