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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [dctQidct/] [Fifo.vhd] - Blame information for rev 145

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1 145 lanttu 
-------------------------------------------------------------------------------
2 
-- File        : fifo.vhdl
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-- Description : Fifo buffer for hibi interface
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-- Author      : Erno Salminen
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-- Date        : 29.04.2002
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-- Modified    : 30.04.2002 Vesa Lahtinen Optimized for synthesis
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--
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-------------------------------------------------------------------------------
9 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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ENTITY Fifo_dct IS
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   GENERIC(
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      width : integer := 0;
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      depth : integer := 0
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   );
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   PORT(
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      Clk            : IN     std_logic;
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      Rst_n          : IN     std_logic;
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      Data_In        : IN     std_logic_vector (width-1 DOWNTO 0);
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      Write_Enable   : IN     std_logic;
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      One_Place_Left : OUT    std_logic;
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      Full           : OUT    std_logic;
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      Data_Out       : OUT    std_logic_vector (width-1 DOWNTO 0);
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      Read_Enable    : IN     std_logic;
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      Empty          : OUT    std_logic;
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      One_Data_Left  : OUT    std_logic
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   );
31 
 
32 
-- Declarations
33 
 
34 
END Fifo_dct ;
35 
 
36 
architecture behavioral of Fifo_dct is
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  type data_array is array (depth-1 downto 0) of std_logic_vector (width-1 downto 0);
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  signal Fifo_Buffer : data_array;
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  signal in_ptr  : integer range 0 to depth-1;
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  signal out_ptr : integer range 0 to depth-1;
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  -- Registers
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  signal Full_reg           : std_logic;
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  signal Empty_reg          : std_logic;
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  signal One_Data_Left_reg  : std_logic;
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  signal One_Place_Left_reg : std_logic;
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  signal Data_Amount        : std_logic_vector (depth-1 downto 0);
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51 
 
52 
begin  -- behavioral
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  -- Continuous assignments
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  -- Assigns register values to outputs
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  Full           <= Full_reg;
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  Empty          <= Empty_reg;
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  One_Data_Left  <= One_Data_Left_reg;
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  One_Place_Left <= One_Place_Left_reg;
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  Data_Out       <= Fifo_Buffer (out_ptr);
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  -- Note! There is some old value in data output when fifo is empty.
62 
 
63 
 
64 
Main : process (Clk, Rst_n)
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begin  -- process Main
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  if Rst_n = '0' then                   -- asynchronous reset (active low)
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    -- Reset all registers
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    -- Fifo is empty at first
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    Full_reg           <= '0';
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    Empty_reg          <= '1';
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    One_Data_Left_reg  <= '0';
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    in_ptr             <= 0;
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    out_ptr            <= 0;
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    Data_Amount        <= (others => '0');
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77 
    if depth =1 then                    -- 30.07
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      One_Place_Left_reg <= '1';
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    else
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      One_Place_Left_reg <= '0';
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    end if;
82 
 
83 
    for i in 0 to depth-1 loop
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      Fifo_Buffer (i)  <= (others => '0');
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    end loop;  -- i
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87 
  elsif Clk'event and Clk = '1' then    -- rising clock edge
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89 
 
90 
    -- 1) Write data to fifo
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    if Write_Enable = '1' and Read_Enable = '0' then
92 
 
93 
      if Full_reg = '0' then
94 
        Empty_reg            <= '0';
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        if (in_ptr = (depth-1)) then
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          in_ptr <= 0;
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        else
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          in_ptr <= in_ptr + 1;
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        end if;
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        out_ptr              <= out_ptr;
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        Data_Amount          <= Data_Amount +1;
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        Fifo_Buffer (in_ptr) <= Data_In;
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        -- Check if the fifo is getting full
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        if Data_Amount + 2 = depth then
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          Full_reg           <= '0';
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          One_Place_Left_reg <= '1';
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        elsif Data_Amount +1 = depth then
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          Full_reg           <= '1';
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          One_Place_Left_reg <= '0';
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        else
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          Full_reg           <= '0';
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          One_Place_Left_reg <= '0';
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        end if;
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        -- If fifo was empty, it has now one data
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        if Empty_reg = '1' then
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          One_Data_Left_reg <= '1';
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        else
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          One_Data_Left_reg <= '0';
121 
        end if;
122 
 
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      else
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        in_ptr             <= in_ptr;
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        out_ptr            <= out_ptr;
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        Full_reg           <= Full_reg;
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        Empty_reg          <= Empty_reg;
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        Fifo_Buffer        <= Fifo_Buffer;
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        Data_Amount        <= Data_Amount;
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        One_Data_Left_reg  <= One_Data_Left_reg;
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        One_Place_Left_reg <= One_Place_Left_reg;
132 
      end if;
133 
 
134 
 
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    -- 2) Read data from fifo
136 
    elsif Write_Enable = '0' and Read_Enable = '1' then
137 
 
138 
      if Empty_reg = '0' then
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        in_ptr      <= in_ptr;
140 
        if (out_ptr = (depth-1)) then
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          out_ptr <= 0;
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        else
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          out_ptr <= out_ptr + 1;
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        end if;
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        Full_reg    <= '0';
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        Data_Amount <= Data_Amount -1;
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        -- Debug
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        -- Fifo_Buffer (out_ptr) <= (others => '1');
150 
 
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        -- Check if the fifo is getting empty
152 
        if Data_Amount = 2 then
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          Empty_reg         <= '0';
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          One_data_Left_reg <= '1';
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        elsif Data_Amount = 1 then
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          Empty_reg         <= '1';
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          One_Data_Left_reg <= '0';
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        else
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          Empty_reg         <= '0';
160 
          One_Data_Left_reg <= '0';
161 
        end if;
162 
 
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        -- If fifo was full, it is no more
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        if Full_reg = '1' then
165 
          One_Place_Left_reg <= '1';
166 
        else
167 
          One_Place_Left_reg <= '0';
168 
        end if;
169 
 
170 
      else
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        in_ptr             <= in_ptr;
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        out_ptr            <= out_ptr;
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        Full_reg           <= Full_reg;
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        Empty_reg          <= Empty_reg;
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        Fifo_Buffer        <= Fifo_Buffer;
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        Data_Amount        <= Data_Amount;
177 
        One_Data_Left_reg  <= One_Data_Left_reg;
178 
        One_Place_Left_reg <= One_Place_Left_reg;
179 
      end if;
180 
 
181 
 
182 
    -- 3) Write and read at the same time
183 
    elsif Write_Enable = '1' and Read_Enable = '1' then
184 
 
185 
 
186 
      if Full_reg = '0' and Empty_reg = '0' then
187 
        if (in_ptr = (depth-1)) then
188 
          in_ptr <= 0;
189 
        else
190 
          in_ptr <= in_ptr + 1;
191 
        end if;
192 
        if (out_ptr = (depth-1)) then
193 
          out_ptr <= 0;
194 
        else
195 
          out_ptr <= out_ptr + 1;
196 
        end if;
197 
        Full_reg           <= '0';
198 
        Empty_reg          <= '0';
199 
        Data_Amount        <= Data_Amount;
200 
        One_Data_Left_reg  <= One_Data_Left_reg;
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        One_Place_Left_reg <= One_Place_Left_reg;
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203 
        Fifo_Buffer (in_ptr)  <= Data_In;
204 
        -- Fifo_Buffer (out_ptr) <= (others => '1');  --debug
205 
 
206 
 
207 
      elsif Full_reg = '1' and Empty_reg = '0' then
208 
        -- Fifo is full, only reading is possible
209 
        in_ptr                <= in_ptr;
210 
        if (out_ptr = (depth-1)) then
211 
          out_ptr <= 0;
212 
        else
213 
          out_ptr <= out_ptr + 1;
214 
        end if;
215 
        Full_reg              <= '0';
216 
        One_Place_Left_reg    <= '1';
217 
        --Fifo_Buffer (out_ptr) <= (others => '1');  -- Debug
218 
        Data_Amount           <= Data_Amount -1;
219 
 
220 
        -- Check if the fifo is getting empty
221 
        if Data_Amount = 2 then
222 
          Empty_reg         <= '0';
223 
          One_data_Left_reg <= '1';
224 
        elsif Data_Amount = 1 then
225 
          Empty_reg         <= '1';
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          One_Data_Left_reg <= '0';
227 
        else
228 
          Empty_reg         <= '0';
229 
          One_Data_Left_reg <= '0';
230 
        end if;
231 
 
232 
 
233 
      elsif Full_reg = '0' and Empty_reg = '1' then
234 
        -- Fifo is empty, only writing is possible
235 
        if (in_ptr = (depth-1)) then
236 
          in_ptr <= 0;
237 
        else
238 
          in_ptr <= in_ptr + 1;
239 
        end if;
240 
        out_ptr              <= out_ptr;
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        Empty_reg            <= '0';
242 
        One_Data_Left_reg    <= '1';
243 
        Fifo_Buffer (in_ptr) <= Data_In;
244 
        Data_Amount          <= Data_Amount +1;
245 
 
246 
        -- Check if the fifo is getting full
247 
        if Data_Amount + 2 = depth then
248 
          Full_reg           <= '0';
249 
          One_Place_Left_reg <= '1';
250 
        elsif Data_Amount +1 = depth then
251 
          Full_reg           <= '1';
252 
          One_Place_Left_reg <= '0';
253 
        else
254 
          Full_reg           <= '0';
255 
          One_Place_Left_reg <= '0';
256 
        end if;
257 
 
258 
 
259 
      -- 4) Do nothing, fifo remains idle
260 
      else
261 
 
262 
        in_ptr             <= in_ptr;
263 
        out_ptr            <= out_ptr;
264 
        Full_reg           <= Full_reg;
265 
        Empty_reg          <= Empty_reg;
266 
        Fifo_Buffer        <= Fifo_Buffer;
267 
        Data_Amount        <= Data_Amount;
268 
        One_Data_Left_reg  <= One_Data_Left_reg;
269 
        One_Place_Left_reg <= One_Place_Left_reg;
270 
      end if;
271 
 
272 
    else
273 
      -- Fifo is idle
274 
      in_ptr             <= in_ptr;
275 
      out_ptr            <= out_ptr;
276 
      Full_reg           <= Full_reg;
277 
      Empty_reg          <= Empty_reg;
278 
      Fifo_Buffer        <= Fifo_Buffer;
279 
      Data_Amount        <= Data_Amount;
280 
      One_Data_Left_reg  <= One_Data_Left_reg;
281 
      One_Place_Left_reg <= One_Place_Left_reg;
282 
    end if;
283 
 
284 
  end if;
285 
end process Main;
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287 
end behavioral;

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