Subversion Repositories funbase_ip_library

------------------------------------------------------------------------------

-- Author        : Timo Alho

-- e-mail        : timo.a.alho@tut.fi

-- Date          : 11.08.2004 13:28:14

-- File          : IDCT1D_DA.vhd

-- Design        : VHDL Entity for idct.IDCT1D_DA.symbol

-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)

------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

LIBRARY idct;

USE idct.IDCT_pkg.all;

LIBRARY common_da;

ENTITY IDCT1D_DA IS

   PORT(

      clk             : IN     std_logic;

      idct_input_data : IN     std_logic_vector (8*IDCT_dataw_co-1 DOWNTO 0);

      last_bit        : IN     std_logic;

      rst_n           : IN     std_logic;

      start           : IN     std_logic;

      idct_out        : OUT    std_logic_vector (8*IDCT_dataw_co-1 DOWNTO 0)

   );

-- Declarations

END IDCT1D_DA ;

------------------------------------------------------------------------------

-- Author        : Timo Alho

-- e-mail        : timo.a.alho@tut.fi

-- Date          : 11.08.2004 13:28:15

-- File          : IDCT1D_DA.vhd

-- Design        : VHDL Architecture for idct.IDCT1D_DA.symbol

-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)

------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

LIBRARY idct;

USE idct.IDCT_pkg.all;

LIBRARY common_da;

ARCHITECTURE struct OF IDCT1D_DA IS

   -- Architecture declarations

   -- Internal signal declarations

   SIGNAL Vec              : std_logic_vector(7 DOWNTO 0);

   SIGNAL VecEven          : std_logic_vector(3 DOWNTO 0);

   SIGNAL VecOdd           : std_logic_vector(3 DOWNTO 0);

   SIGNAL coeff_even       : std_logic_vector(4*IDCT_coeffw_co-1 DOWNTO 0);

   SIGNAL coeff_odd        : std_logic_vector(4*IDCT_coeffw_co-1 DOWNTO 0);

   SIGNAL mult_to_post_sum : std_logic_vector(8*IDCT_dataw_co-1 DOWNTO 0);

   SIGNAL start_mul        : std_logic;

   -- ModuleWare signal declarations(v1.0) for instance 'I7' of 'adff'

   SIGNAL mw_I7creg : std_logic := '0';

   -- Component Declarations

   COMPONENT Parallel2Serial

   GENERIC (

      dataw_g : integer := 18

   );

   PORT (

      clk   : IN     std_logic ;

      d_in  : IN     std_logic_vector (dataw_g-1 DOWNTO 0); --parallel input data

      load  : IN     std_logic ;                            --'1' => d_in is loaded in

      rst_n : IN     std_logic ;

      d_out : OUT    std_logic                              --serial output data

   );

   END COMPONENT;

   COMPONENT Serial_multiplier4idct

   GENERIC (

      coeffw_g    : integer := 14;

      i_dataw_g   : integer := 18;

      round_val_g : integer := 64

   );

   PORT (

      clk        : IN     std_logic ;

      last_value : IN     std_logic ;

      mul_in     : IN     std_logic_vector (coeffw_g-1 DOWNTO 0);

      rst_n      : IN     std_logic ;

      start      : IN     std_logic ;

      mul_out    : OUT    std_logic_vector (i_dataw_g-1 DOWNTO 0)

   );

   END COMPONENT;

   COMPONENT IDCT_post_sum

   PORT (

      post_sum_in  : IN     std_logic_vector (8*IDCT_dataw_co-1 DOWNTO 0);

      post_sum_out : OUT    std_logic_vector (8*IDCT_dataw_co-1 DOWNTO 0)

   );

   END COMPONENT;

   COMPONENT Rom_idct_even

   GENERIC (

      coeffw_g : integer := 14

   );

   PORT (

      addr_in  : IN     std_logic_vector (3 DOWNTO 0);

      clk      : IN     std_logic ;

      data_out : OUT    std_logic_vector (4*coeffw_g-1 DOWNTO 0)

   );

   END COMPONENT;

   COMPONENT Rom_idct_odd

   GENERIC (

      coeffw_g : integer := 14

   );

   PORT (

      addr_in  : IN     std_logic_vector (3 DOWNTO 0);

      clk      : IN     std_logic ;

      data_out : OUT    std_logic_vector (4*coeffw_g-1 DOWNTO 0)

   );

   END COMPONENT;

BEGIN

   -- Architecture concurrent statements

   -- HDL Embedded Text Block 1 eb1

   -- eb1 1                           

   VecOdd <=Vec(6)&Vec(4)&Vec(2)&Vec(0);

   VecEven<=Vec(7) &Vec(5)&Vec(3)&Vec(1);

   -- ModuleWare code(v1.0) for instance 'I7' of 'adff'

   start_mul <= mw_I7creg;

   -- exemplar async_set_reset_local of I7seq "rst_n"

   I7seq: PROCESS (clk, rst_n)

   BEGIN

      IF (rst_n = '0' OR rst_n = 'L') THEN

         mw_I7creg <= '0';

      ELSIF (clk'EVENT AND clk='1') THEN

         mw_I7creg <= start;

      END IF;

   END PROCESS I7seq;

   -- Instance port mappings.

   post_sum : IDCT_post_sum

      PORT MAP (

         post_sum_in  => mult_to_post_sum,

         post_sum_out => idct_out

      );

   eventerm_rom : Rom_idct_even

      GENERIC MAP (

         coeffw_g => IDCT_coeffw_co

      )

      PORT MAP (

         addr_in  => VecEven,

         clk      => clk,

         data_out => coeff_even

      );

   oddterm_rom : Rom_idct_odd

      GENERIC MAP (

         coeffw_g => IDCT_coeffw_co

      )

      PORT MAP (

         addr_in  => VecOdd,

         clk      => clk,

         data_out => coeff_odd

      );

   g1: FOR i IN 0 TO 7 GENERATE

      input_p2s : Parallel2Serial

         GENERIC MAP (

            dataw_g => IDCT_dataw_co

         )

         PORT MAP (

            clk=>clk,

            rst_n=>rst_n,

            load=>start,

            d_in=>idct_input_data((i+1)*IDCT_dataw_co-1 DOWNTO i*IDCT_dataw_co),

            d_out => Vec(i)

         );

   END GENERATE g1;

   g4: FOR i IN 0 TO 3 GENERATE

      oddterm_mul : Serial_multiplier4idct

         GENERIC MAP (

            coeffw_g    => IDCT_coeffw_co,

            i_dataw_g   => IDCT_dataw_co,

            round_val_g => IDCT_rounding_value_co

         )

         PORT MAP (

            clk=>clk,

            rst_n=>rst_n,

            last_value=>last_bit,

            start=>start_mul,

            mul_out=>mult_to_post_sum((i+1)*IDCT_dataw_co-1 DOWNTO i*IDCT_dataw_co),

            mul_in=>coeff_odd((4-i)*IDCT_coeffw_co-1 DOWNTO (3-i)*IDCT_coeffw_co)

         );

   END GENERATE g4;

   g5: FOR i IN 0 TO 3 GENERATE

      eventerm_mul : Serial_multiplier4idct

         GENERIC MAP (

            coeffw_g    => IDCT_coeffw_co,

            i_dataw_g   => IDCT_dataw_co,

            round_val_g => IDCT_rounding_value_co

         )

         PORT MAP (

            clk=>clk,

            rst_n=>rst_n,

            last_value=>last_bit,

            start=>start_mul,

            mul_out=>mult_to_post_sum((4+i+1)*IDCT_dataw_co-1 DOWNTO (4+i)*IDCT_dataw_co),

            mul_in=>coeff_even((4-i)*IDCT_coeffw_co-1 DOWNTO (3-i)*IDCT_coeffw_co)

         );

   END GENERATE g5;

END struct;