URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [idct/] [IDCT_control.vhd] - Blame information for rev 145

Details | Compare with Previous | View Log


------------------------------------------------------------------------------
-- Author        : Timo Alho
-- e-mail        : timo.a.alho@tut.fi
-- Date          : 11.08.2004 13:28:13
-- File          : IDCT_control.vhd
-- Design        : VHDL Entity for idct.IDCT_control.symbol
-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)
------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY idct;
USE idct.IDCT_pkg.all;
LIBRARY common_da;
 
ENTITY IDCT_control IS
   PORT(
      clk              : IN     std_logic;
      next_block_ready : IN     std_logic;
      rst_n            : IN     std_logic;
      wr_new_data      : IN     std_logic;
      load_input       : OUT    std_logic;
      load_output      : OUT    std_logic;
      out_clk_en       : OUT    std_logic;
      rdaddr           : OUT    std_logic_vector (5 DOWNTO 0);
      ready_for_rx     : OUT    std_logic;
      sel_input        : OUT    std_logic;
      start_idct       : OUT    std_logic;
      stop_idct        : OUT    std_logic;
      we               : OUT    std_logic;
      wr_out           : OUT    std_logic;
      wraddr           : OUT    std_logic_vector (5 DOWNTO 0)
   );
 
-- Declarations
 
END IDCT_control ;
 
------------------------------------------------------------------------------
-- Author        : Timo Alho
-- e-mail        : timo.a.alho@tut.fi
-- Date          : 11.08.2004 13:28:13
-- File          : IDCT_control.vhd
-- Design        : VHDL Architecture for idct.IDCT_control.symbol
-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)
------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY idct;
USE idct.IDCT_pkg.all;
 
ARCHITECTURE fsm OF IDCT_control IS
 
   -- Architecture Declarations
   signal wait_counter_r : unsigned (4 downto 0);
   signal col_nr_r : unsigned(2 downto 0);
   signal row_rd_nr_r : unsigned(2 downto 0);
   signal row_wr_nr_r : unsigned(2 downto 0);
 
   signal in_counter_r : unsigned(2 downto 0);
   --signal in_counter_next : unsigned(2 downto 0);
 
   signal out_counter_r : unsigned(2 downto 0);
   --signal out_counter_next : unsigned(2 downto 0);
 
   signal output_ready : std_logic;
 
   signal load_rows : std_logic;
   signal load_columns : std_logic;
   signal save_result : std_logic;
   signal result_out : std_logic;
   signal col_ready : std_logic;
 
   TYPE CSM_STATE_TYPE IS (
      start_fsm,
      start_col_calc,
      wait_col_calc,
      stop_last_row,
      wait_row_calc,
      wait_data,
      stop_and_start_next_col,
      stop_col_calc,
      stop_last_col,
      dummy0,
      start_row_calc,
      stop_row_calc,
      wait_output_free,
      stop_and_start_next_row,
      dummy1,
      wt_nxt
   );
   TYPE CSM1_STATE_TYPE IS (
      o_ready,
      wr_col_to_ram,
      result_to_buffer,
      result_to_buffer2,
      res_out1,
      wait_output
   );
   TYPE CSM2_STATE_TYPE IS (
      i_ready,
      i_load_row,
      i_load_column,
      wait_ram_rd,
      wait_load,
      wait_1st_column
   );
 
 
   -- Declare current and next state signals
   SIGNAL csm_current_state : CSM_STATE_TYPE ;
   SIGNAL csm_next_state : CSM_STATE_TYPE ;
   SIGNAL csm1_current_state : CSM1_STATE_TYPE ;
   SIGNAL csm1_next_state : CSM1_STATE_TYPE ;
   SIGNAL csm2_current_state : CSM2_STATE_TYPE ;
   SIGNAL csm2_next_state : CSM2_STATE_TYPE ;
 
   -- Declare any pre-registered internal signals
   SIGNAL wr_out_int : std_logic  ;
 
BEGIN
 
   ----------------------------------------------------------------------------
   csm_clocked : PROCESS(
      clk,
      rst_n
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (rst_n = '0') THEN
         csm_current_state <= start_fsm;
         -- Reset Values
         col_nr_r <= (others => '0');
         row_rd_nr_r <= (others => '0');
         row_wr_nr_r <= (others => '0');
         wait_counter_r <= (others => '0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         csm_current_state <= csm_next_state;
         -- Default Assignment To Internals
 
         -- Combined Actions for internal signals only
         CASE csm_current_state IS
         WHEN start_col_calc =>
            wait_counter_r <= (others => '0');
         WHEN wait_col_calc =>
            row_rd_nr_r <= (others => '0');
            wait_counter_r <= wait_counter_r + 1;
         WHEN stop_last_row =>
            row_rd_nr_r <= (others => '0');
            col_nr_r <= (others => '0');
         WHEN wait_row_calc =>
            --wait until row is processed
            wait_counter_r <= wait_counter_r + 1;
         WHEN stop_and_start_next_col =>
            col_nr_r <= col_nr_r + 1;
            row_wr_nr_r <= col_nr_r;
            wait_counter_r <= (others => '0');
         WHEN stop_col_calc =>
            col_nr_r <= col_nr_r + 1;
            row_wr_nr_r <= col_nr_r;
         WHEN stop_last_col =>
            col_nr_r <= (others => '0');
            row_wr_nr_r <= col_nr_r;
            wait_counter_r <= (others => '0');
         WHEN dummy0 =>
            --wait until last element of first row is read from memory
            wait_counter_r <= wait_counter_r+1;
         WHEN start_row_calc =>
            row_rd_nr_r <= row_rd_nr_r + 1;
            wait_counter_r <= (others => '0');
         WHEN stop_row_calc =>
            --stop calculation of current row
            col_nr_r <= col_nr_r + 1;
         WHEN stop_and_start_next_row =>
            row_rd_nr_r <= row_rd_nr_r + 1;
            col_nr_r <= col_nr_r + 1;
            wait_counter_r <= (others => '0');
         WHEN OTHERS =>
            NULL;
         END CASE;
 
      END IF;
 
   END PROCESS csm_clocked;
 
   ----------------------------------------------------------------------------
   csm_nextstate : PROCESS (
      col_nr_r,
      col_ready,
      csm_current_state,
      next_block_ready,
      wait_counter_r
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE csm_current_state IS
      WHEN start_fsm =>
            csm_next_state <= wait_data;
      WHEN start_col_calc =>
            csm_next_state <= wait_col_calc;
      WHEN wait_col_calc =>
         IF (col_nr_r =7 AND
         wait_counter_r = IDCT_inputw_co) THEN
            csm_next_state <= stop_last_col;
         ELSIF (col_ready = '1' AND
         wait_counter_r = IDCT_inputw_co) THEN
            csm_next_state <= stop_and_start_next_col;
         ELSIF (wait_counter_r = IDCT_inputw_co) THEN
            csm_next_state <= stop_col_calc;
         ELSE
            csm_next_state <= wait_col_calc;
         END IF;
      WHEN stop_last_row =>
         IF (col_ready = '1' AND next_block_ready = '1') THEN
            csm_next_state <= start_col_calc;
         ELSE
            csm_next_state <= wt_nxt;
         END IF;
      WHEN wait_row_calc =>
         IF (wait_counter_r = IDCT_dataw_co AND
         col_nr_r = 7) THEN
            csm_next_state <= stop_last_row;
         ELSIF (wait_counter_r = IDCT_dataw_co AND
         next_block_ready = '1') THEN
            csm_next_state <= stop_and_start_next_row;
         ELSIF (wait_counter_r = IDCT_dataw_co) THEN
            csm_next_state <= stop_row_calc;
         ELSE
            csm_next_state <= wait_row_calc;
         END IF;
      WHEN wait_data =>
         IF (col_ready = '1') THEN
            csm_next_state <= start_col_calc;
         ELSE
            csm_next_state <= wait_data;
         END IF;
      WHEN stop_and_start_next_col =>
            csm_next_state <= wait_col_calc;
      WHEN stop_col_calc =>
         IF (col_ready = '1') THEN
            csm_next_state <= start_col_calc;
         ELSE
            csm_next_state <= wait_data;
         END IF;
      WHEN stop_last_col =>
            csm_next_state <= dummy0;
      WHEN dummy0 =>
         IF (wait_counter_r = 2) THEN
            csm_next_state <= dummy1;
         ELSE
            csm_next_state <= dummy0;
         END IF;
      WHEN start_row_calc =>
            csm_next_state <= wait_row_calc;
      WHEN stop_row_calc =>
            csm_next_state <= wait_output_free;
      WHEN wait_output_free =>
         IF (next_block_ready = '1') THEN
            csm_next_state <= start_row_calc;
         ELSE
            csm_next_state <= wait_output_free;
         END IF;
      WHEN stop_and_start_next_row =>
            csm_next_state <= wait_row_calc;
      WHEN dummy1 =>
         IF (next_block_ready = '1') THEN
            csm_next_state <= start_row_calc;
         ELSE
            csm_next_state <= dummy1;
         END IF;
      WHEN wt_nxt =>
         IF (next_block_ready = '1') THEN
            csm_next_state <= wait_data;
         ELSE
            csm_next_state <= wt_nxt;
         END IF;
      WHEN OTHERS =>
         csm_next_state <= start_fsm;
      END CASE;
 
   END PROCESS csm_nextstate;
 
   ----------------------------------------------------------------------------
   csm_output : PROCESS (
      col_nr_r,
      csm_current_state,
      wait_counter_r
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      start_idct <= '0';
      stop_idct <= '0';
      -- Default Assignment To Internals
      load_columns <= '0';
      load_rows <= '0';
      result_out <= '0';
      save_result <= '0';
 
      -- Combined Actions
      CASE csm_current_state IS
      WHEN start_fsm =>
         load_columns <= '1';
      WHEN start_col_calc =>
         --start calculation of column
         start_idct <= '1';
         if (col_nr_r /= 7) then
         load_columns <= '1';
         end if;
      WHEN wait_col_calc =>
         --wait few clock cycles while column is being processed
         if (col_nr_r = 7 AND wait_counter_r = 8) then
         --last column is being processed so we can start loading input "buffer" with values of first row
         load_rows <= '1';
         end if;
      WHEN stop_last_row =>
         --stop calculation of the last row
         stop_idct <= '1';
         result_out <= '1';
      WHEN wait_data =>
         --wait until there is new data available
      WHEN stop_and_start_next_col =>
         --stop calculation of current column, and start calculation of next column
         if (col_nr_r /=6) then
         load_columns <= '1';
         end if;
         start_idct <=  '1';
         stop_idct <= '1';
         save_result <= '1';
      WHEN stop_col_calc =>
         --stop calculation of current column
         stop_idct <= '1';
         save_result <= '1';
      WHEN stop_last_col =>
         --stop calculation of last column
         stop_idct <= '1';
         save_result <= '1';
      WHEN start_row_calc =>
         --start calculation of row
         start_idct <= '1';
         if (col_nr_r /=7) then
           load_rows <= '1';
         else
           load_columns <= '1';
         end if;
      WHEN stop_row_calc =>
         stop_idct <= '1';
         result_out <= '1';
      WHEN wait_output_free =>
         --we must wait until next block is capable of receiving data
      WHEN stop_and_start_next_row =>
         --stop calculation of current row, and start next row
         start_idct <= '1';
         stop_idct <= '1';
         result_out <= '1';
         if (col_nr_r /= 6) then
           load_rows <= '1';
         else
           load_columns <= '1';
         end if;
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS csm_output;
 
   ----------------------------------------------------------------------------
   csm1_clocked : PROCESS(
      clk,
      rst_n
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (rst_n = '0') THEN
         csm1_current_state <= o_ready;
         -- Reset Values
         wr_out <= '0';
         out_counter_r <= (others => '0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         csm1_current_state <= csm1_next_state;
         -- Registered output assignments
         wr_out <= wr_out_int;
 
         -- Default Assignment To Internals
 
         -- Combined Actions for internal signals only
         CASE csm1_current_state IS
         WHEN o_ready =>
            out_counter_r <= (others => '0');
         WHEN wr_col_to_ram =>
            out_counter_r <= out_counter_r + 1;
         WHEN res_out1 =>
            out_counter_r <= out_counter_r + 1;
         WHEN OTHERS =>
            NULL;
         END CASE;
 
      END IF;
 
   END PROCESS csm1_clocked;
 
   ----------------------------------------------------------------------------
   csm1_nextstate : PROCESS (
      csm1_current_state,
      next_block_ready,
      out_counter_r,
      result_out,
      save_result
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE csm1_current_state IS
      WHEN o_ready =>
         IF (save_result = '1') THEN
            csm1_next_state <= result_to_buffer;
         ELSIF (result_out = '1') THEN
            csm1_next_state <= result_to_buffer2;
         ELSE
            csm1_next_state <= o_ready;
         END IF;
      WHEN wr_col_to_ram =>
         IF (out_counter_r = 7) THEN
            csm1_next_state <= o_ready;
         ELSE
            csm1_next_state <= wr_col_to_ram;
         END IF;
      WHEN result_to_buffer =>
            csm1_next_state <= wr_col_to_ram;
      WHEN result_to_buffer2 =>
         IF (next_block_ready = '1') THEN
            csm1_next_state <= res_out1;
         ELSE
            csm1_next_state <= wait_output;
         END IF;
      WHEN res_out1 =>
         IF (out_counter_r = 7) THEN
            csm1_next_state <= o_ready;
         ELSE
            csm1_next_state <= res_out1;
         END IF;
      WHEN wait_output =>
         IF (next_block_ready = '1') THEN
            csm1_next_state <= res_out1;
         ELSE
            csm1_next_state <= wait_output;
         END IF;
      WHEN OTHERS =>
         csm1_next_state <= o_ready;
      END CASE;
 
   END PROCESS csm1_nextstate;
 
   ----------------------------------------------------------------------------
   csm1_output : PROCESS (
      csm1_current_state
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      load_output <= '0';
      out_clk_en <= '0';
      we <= '0';
      wr_out_int <= '0';
      -- Default Assignment To Internals
      output_ready <= '0';
 
      -- Combined Actions
      CASE csm1_current_state IS
      WHEN o_ready =>
         output_ready <= '1';
      WHEN wr_col_to_ram =>
         we <= '1';
         out_clk_en <= '1';
      WHEN result_to_buffer =>
         load_output <= '1';
      WHEN result_to_buffer2 =>
         load_output <= '1';
      WHEN res_out1 =>
         out_clk_en <= '1';
         wr_out_int <= '1';
         --if (col_nr_r = 1 AND out_counter_r = 0) then
         --DC <= '1';
         --end if;
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS csm1_output;
 
   ----------------------------------------------------------------------------
   csm2_clocked : PROCESS(
      clk,
      rst_n
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (rst_n = '0') THEN
         csm2_current_state <= i_ready;
         -- Reset Values
         in_counter_r <= (others => '0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         csm2_current_state <= csm2_next_state;
         -- Default Assignment To Internals
 
         -- Combined Actions for internal signals only
         CASE csm2_current_state IS
         WHEN i_ready =>
            in_counter_r <= (OTHERS => '0');
         WHEN i_load_row =>
            in_counter_r <= in_counter_r + 1;
         WHEN i_load_column =>
            if (wr_new_data = '1') then
              in_counter_r <= in_counter_r + 1;
            end if;
         WHEN wait_ram_rd =>
            in_counter_r <= in_counter_r + 1;
         WHEN wait_1st_column =>
            if (wr_new_data = '1') then
             in_counter_r <= in_counter_r + 1;
            end if;
         WHEN OTHERS =>
            NULL;
         END CASE;
 
      END IF;
 
   END PROCESS csm2_clocked;
 
   ----------------------------------------------------------------------------
   csm2_nextstate : PROCESS (
      csm2_current_state,
      in_counter_r,
      load_columns,
      load_rows,
      wr_new_data
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE csm2_current_state IS
      WHEN i_ready =>
         IF (load_columns = '1') THEN
            csm2_next_state <= wait_1st_column;
         ELSIF (load_rows = '1') THEN
            csm2_next_state <= wait_ram_rd;
         ELSE
            csm2_next_state <= i_ready;
         END IF;
      WHEN i_load_row =>
         IF (in_counter_r = 7) THEN
            csm2_next_state <= wait_load;
         ELSE
            csm2_next_state <= i_load_row;
         END IF;
      WHEN i_load_column =>
         IF (in_counter_r = 7 AND wr_new_data = '1') THEN
            csm2_next_state <= i_ready;
         ELSE
            csm2_next_state <= i_load_column;
         END IF;
      WHEN wait_ram_rd =>
            csm2_next_state <= i_load_row;
      WHEN wait_load =>
            csm2_next_state <= i_ready;
      WHEN wait_1st_column =>
         IF (wr_new_data = '1') THEN
            csm2_next_state <= i_load_column;
         ELSE
            csm2_next_state <= wait_1st_column;
         END IF;
      WHEN OTHERS =>
         csm2_next_state <= i_ready;
      END CASE;
 
   END PROCESS csm2_nextstate;
 
   ----------------------------------------------------------------------------
   csm2_output : PROCESS (
      csm2_current_state,
      wr_new_data
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      load_input <= '0';
      ready_for_rx <= '0';
      sel_input <= '0';
      -- Default Assignment To Internals
      col_ready <= '0';
 
      -- Combined Actions
      CASE csm2_current_state IS
      WHEN i_ready =>
         col_ready <= '1';
      WHEN i_load_row =>
         sel_input <= '0'; -- load data from ram
         load_input <= '1';
      WHEN i_load_column =>
         sel_input <= '1';
         if (wr_new_data = '1') then
           load_input <= '1';
         end if;
      WHEN wait_ram_rd =>
         sel_input <= '0';
      WHEN wait_load =>
         sel_input <= '0';
         load_input <= '1';
      WHEN wait_1st_column =>
         sel_input <= '1';
         ready_for_rx <= '1';
         if (wr_new_data = '1') then
          load_input <= '1';
         end if;
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS csm2_output;
 
   -- Concurrent Statements
wraddr <= conv_std_logic_vector(row_wr_nr_r & out_counter_r, 6);
rdaddr <= conv_std_logic_vector(in_counter_r & row_rd_nr_r, 6);
 
END fsm;

Browse

Tools

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [idct/] [IDCT_control.vhd] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu	`------------------------------------------------------------------------------`
2			`-- Author : Timo Alho`
3			`-- e-mail : timo.a.alho@tut.fi`
4			`-- Date : 11.08.2004 13:28:13`
5			`-- File : IDCT_control.vhd`
6			`-- Design : VHDL Entity for idct.IDCT_control.symbol`
7			`-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)`
8			`------------------------------------------------------------------------------`
9			`LIBRARY ieee;`
10			`USE ieee.std_logic_1164.all;`
11			`USE ieee.std_logic_arith.all;`
12			`LIBRARY idct;`
13			`USE idct.IDCT_pkg.all;`
14			`LIBRARY common_da;`
15
16			`ENTITY IDCT_control IS`
17			`PORT(`
18			`clk : IN std_logic;`
19			`next_block_ready : IN std_logic;`
20			`rst_n : IN std_logic;`
21			`wr_new_data : IN std_logic;`
22			`load_input : OUT std_logic;`
23			`load_output : OUT std_logic;`
24			`out_clk_en : OUT std_logic;`
25			`rdaddr : OUT std_logic_vector (5 DOWNTO 0);`
26			`ready_for_rx : OUT std_logic;`
27			`sel_input : OUT std_logic;`
28			`start_idct : OUT std_logic;`
29			`stop_idct : OUT std_logic;`
30			`we : OUT std_logic;`
31			`wr_out : OUT std_logic;`
32			`wraddr : OUT std_logic_vector (5 DOWNTO 0)`
33			`);`
34
35			`-- Declarations`
36
37			`END IDCT_control ;`
38
39			`------------------------------------------------------------------------------`
40			`-- Author : Timo Alho`
41			`-- e-mail : timo.a.alho@tut.fi`
42			`-- Date : 11.08.2004 13:28:13`
43			`-- File : IDCT_control.vhd`
44			`-- Design : VHDL Architecture for idct.IDCT_control.symbol`
45			`-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)`
46			`------------------------------------------------------------------------------`
47			`LIBRARY ieee;`
48			`USE ieee.std_logic_1164.all;`
49			`USE ieee.std_logic_arith.all;`
50			`LIBRARY idct;`
51			`USE idct.IDCT_pkg.all;`
52
53			`ARCHITECTURE fsm OF IDCT_control IS`
54
55			`-- Architecture Declarations`
56			`signal wait_counter_r : unsigned (4 downto 0);`
57			`signal col_nr_r : unsigned(2 downto 0);`
58			`signal row_rd_nr_r : unsigned(2 downto 0);`
59			`signal row_wr_nr_r : unsigned(2 downto 0);`
60
61			`signal in_counter_r : unsigned(2 downto 0);`
62			`--signal in_counter_next : unsigned(2 downto 0);`
63
64			`signal out_counter_r : unsigned(2 downto 0);`
65			`--signal out_counter_next : unsigned(2 downto 0);`
66
67			`signal output_ready : std_logic;`
68
69			`signal load_rows : std_logic;`
70			`signal load_columns : std_logic;`
71			`signal save_result : std_logic;`
72			`signal result_out : std_logic;`
73			`signal col_ready : std_logic;`
74
75			`TYPE CSM_STATE_TYPE IS (`
76			`start_fsm,`
77			`start_col_calc,`
78			`wait_col_calc,`
79			`stop_last_row,`
80			`wait_row_calc,`
81			`wait_data,`
82			`stop_and_start_next_col,`
83			`stop_col_calc,`
84			`stop_last_col,`
85			`dummy0,`
86			`start_row_calc,`
87			`stop_row_calc,`
88			`wait_output_free,`
89			`stop_and_start_next_row,`
90			`dummy1,`
91			`wt_nxt`
92			`);`
93			`TYPE CSM1_STATE_TYPE IS (`
94			`o_ready,`
95			`wr_col_to_ram,`
96			`result_to_buffer,`
97			`result_to_buffer2,`
98			`res_out1,`
99			`wait_output`
100			`);`
101			`TYPE CSM2_STATE_TYPE IS (`
102			`i_ready,`
103			`i_load_row,`
104			`i_load_column,`
105			`wait_ram_rd,`
106			`wait_load,`
107			`wait_1st_column`
108			`);`
109
110
111			`-- Declare current and next state signals`
112			`SIGNAL csm_current_state : CSM_STATE_TYPE ;`
113			`SIGNAL csm_next_state : CSM_STATE_TYPE ;`
114			`SIGNAL csm1_current_state : CSM1_STATE_TYPE ;`
115			`SIGNAL csm1_next_state : CSM1_STATE_TYPE ;`
116			`SIGNAL csm2_current_state : CSM2_STATE_TYPE ;`
117			`SIGNAL csm2_next_state : CSM2_STATE_TYPE ;`
118
119			`-- Declare any pre-registered internal signals`
120			`SIGNAL wr_out_int : std_logic ;`
121
122			`BEGIN`
123
124			`----------------------------------------------------------------------------`
125			`csm_clocked : PROCESS(`
126			`clk,`
127			`rst_n`
128			`)`
129			`----------------------------------------------------------------------------`
130			`BEGIN`
131			`IF (rst_n = '0') THEN`
132			`csm_current_state <= start_fsm;`
133			`-- Reset Values`
134			`col_nr_r <= (others => '0');`
135			`row_rd_nr_r <= (others => '0');`
136			`row_wr_nr_r <= (others => '0');`
137			`wait_counter_r <= (others => '0');`
138			`ELSIF (clk'EVENT AND clk = '1') THEN`
139			`csm_current_state <= csm_next_state;`
140			`-- Default Assignment To Internals`
141
142			`-- Combined Actions for internal signals only`
143			`CASE csm_current_state IS`
144			`WHEN start_col_calc =>`
145			`wait_counter_r <= (others => '0');`
146			`WHEN wait_col_calc =>`
147			`row_rd_nr_r <= (others => '0');`
148			`wait_counter_r <= wait_counter_r + 1;`
149			`WHEN stop_last_row =>`
150			`row_rd_nr_r <= (others => '0');`
151			`col_nr_r <= (others => '0');`
152			`WHEN wait_row_calc =>`
153			`--wait until row is processed`
154			`wait_counter_r <= wait_counter_r + 1;`
155			`WHEN stop_and_start_next_col =>`
156			`col_nr_r <= col_nr_r + 1;`
157			`row_wr_nr_r <= col_nr_r;`
158			`wait_counter_r <= (others => '0');`
159			`WHEN stop_col_calc =>`
160			`col_nr_r <= col_nr_r + 1;`
161			`row_wr_nr_r <= col_nr_r;`
162			`WHEN stop_last_col =>`
163			`col_nr_r <= (others => '0');`
164			`row_wr_nr_r <= col_nr_r;`
165			`wait_counter_r <= (others => '0');`
166			`WHEN dummy0 =>`
167			`--wait until last element of first row is read from memory`
168			`wait_counter_r <= wait_counter_r+1;`
169			`WHEN start_row_calc =>`
170			`row_rd_nr_r <= row_rd_nr_r + 1;`
171			`wait_counter_r <= (others => '0');`
172			`WHEN stop_row_calc =>`
173			`--stop calculation of current row`
174			`col_nr_r <= col_nr_r + 1;`
175			`WHEN stop_and_start_next_row =>`
176			`row_rd_nr_r <= row_rd_nr_r + 1;`
177			`col_nr_r <= col_nr_r + 1;`
178			`wait_counter_r <= (others => '0');`
179			`WHEN OTHERS =>`
180			`NULL;`
181			`END CASE;`
182
183			`END IF;`
184
185			`END PROCESS csm_clocked;`
186
187			`----------------------------------------------------------------------------`
188			`csm_nextstate : PROCESS (`
189			`col_nr_r,`
190			`col_ready,`
191			`csm_current_state,`
192			`next_block_ready,`
193			`wait_counter_r`
194			`)`
195			`----------------------------------------------------------------------------`
196			`BEGIN`
197			`CASE csm_current_state IS`
198			`WHEN start_fsm =>`
199			`csm_next_state <= wait_data;`
200			`WHEN start_col_calc =>`
201			`csm_next_state <= wait_col_calc;`
202			`WHEN wait_col_calc =>`
203			`IF (col_nr_r =7 AND`
204			`wait_counter_r = IDCT_inputw_co) THEN`
205			`csm_next_state <= stop_last_col;`
206			`ELSIF (col_ready = '1' AND`
207			`wait_counter_r = IDCT_inputw_co) THEN`
208			`csm_next_state <= stop_and_start_next_col;`
209			`ELSIF (wait_counter_r = IDCT_inputw_co) THEN`
210			`csm_next_state <= stop_col_calc;`
211			`ELSE`
212			`csm_next_state <= wait_col_calc;`
213			`END IF;`
214			`WHEN stop_last_row =>`
215			`IF (col_ready = '1' AND next_block_ready = '1') THEN`
216			`csm_next_state <= start_col_calc;`
217			`ELSE`
218			`csm_next_state <= wt_nxt;`
219			`END IF;`
220			`WHEN wait_row_calc =>`
221			`IF (wait_counter_r = IDCT_dataw_co AND`
222			`col_nr_r = 7) THEN`
223			`csm_next_state <= stop_last_row;`
224			`ELSIF (wait_counter_r = IDCT_dataw_co AND`
225			`next_block_ready = '1') THEN`
226			`csm_next_state <= stop_and_start_next_row;`
227			`ELSIF (wait_counter_r = IDCT_dataw_co) THEN`
228			`csm_next_state <= stop_row_calc;`
229			`ELSE`
230			`csm_next_state <= wait_row_calc;`
231			`END IF;`
232			`WHEN wait_data =>`
233			`IF (col_ready = '1') THEN`
234			`csm_next_state <= start_col_calc;`
235			`ELSE`
236			`csm_next_state <= wait_data;`
237			`END IF;`
238			`WHEN stop_and_start_next_col =>`
239			`csm_next_state <= wait_col_calc;`
240			`WHEN stop_col_calc =>`
241			`IF (col_ready = '1') THEN`
242			`csm_next_state <= start_col_calc;`
243			`ELSE`
244			`csm_next_state <= wait_data;`
245			`END IF;`
246			`WHEN stop_last_col =>`
247			`csm_next_state <= dummy0;`
248			`WHEN dummy0 =>`
249			`IF (wait_counter_r = 2) THEN`
250			`csm_next_state <= dummy1;`
251			`ELSE`
252			`csm_next_state <= dummy0;`
253			`END IF;`
254			`WHEN start_row_calc =>`
255			`csm_next_state <= wait_row_calc;`
256			`WHEN stop_row_calc =>`
257			`csm_next_state <= wait_output_free;`
258			`WHEN wait_output_free =>`
259			`IF (next_block_ready = '1') THEN`
260			`csm_next_state <= start_row_calc;`
261			`ELSE`
262			`csm_next_state <= wait_output_free;`
263			`END IF;`
264			`WHEN stop_and_start_next_row =>`
265			`csm_next_state <= wait_row_calc;`
266			`WHEN dummy1 =>`
267			`IF (next_block_ready = '1') THEN`
268			`csm_next_state <= start_row_calc;`
269			`ELSE`
270			`csm_next_state <= dummy1;`
271			`END IF;`
272			`WHEN wt_nxt =>`
273			`IF (next_block_ready = '1') THEN`
274			`csm_next_state <= wait_data;`
275			`ELSE`
276			`csm_next_state <= wt_nxt;`
277			`END IF;`
278			`WHEN OTHERS =>`
279			`csm_next_state <= start_fsm;`
280			`END CASE;`
281
282			`END PROCESS csm_nextstate;`
283
284			`----------------------------------------------------------------------------`
285			`csm_output : PROCESS (`
286			`col_nr_r,`
287			`csm_current_state,`
288			`wait_counter_r`
289			`)`
290			`----------------------------------------------------------------------------`
291			`BEGIN`
292			`-- Default Assignment`
293			`start_idct <= '0';`
294			`stop_idct <= '0';`
295			`-- Default Assignment To Internals`
296			`load_columns <= '0';`
297			`load_rows <= '0';`
298			`result_out <= '0';`
299			`save_result <= '0';`
300
301			`-- Combined Actions`
302			`CASE csm_current_state IS`
303			`WHEN start_fsm =>`
304			`load_columns <= '1';`
305			`WHEN start_col_calc =>`
306			`--start calculation of column`
307			`start_idct <= '1';`
308			`if (col_nr_r /= 7) then`
309			`load_columns <= '1';`
310			`end if;`
311			`WHEN wait_col_calc =>`
312			`--wait few clock cycles while column is being processed`
313			`if (col_nr_r = 7 AND wait_counter_r = 8) then`
314			`--last column is being processed so we can start loading input "buffer" with values of first row`
315			`load_rows <= '1';`
316			`end if;`
317			`WHEN stop_last_row =>`
318			`--stop calculation of the last row`
319			`stop_idct <= '1';`
320			`result_out <= '1';`
321			`WHEN wait_data =>`
322			`--wait until there is new data available`
323			`WHEN stop_and_start_next_col =>`
324			`--stop calculation of current column, and start calculation of next column`
325			`if (col_nr_r /=6) then`
326			`load_columns <= '1';`
327			`end if;`
328			`start_idct <= '1';`
329			`stop_idct <= '1';`
330			`save_result <= '1';`
331			`WHEN stop_col_calc =>`
332			`--stop calculation of current column`
333			`stop_idct <= '1';`
334			`save_result <= '1';`
335			`WHEN stop_last_col =>`
336			`--stop calculation of last column`
337			`stop_idct <= '1';`
338			`save_result <= '1';`
339			`WHEN start_row_calc =>`
340			`--start calculation of row`
341			`start_idct <= '1';`
342			`if (col_nr_r /=7) then`
343			`load_rows <= '1';`
344			`else`
345			`load_columns <= '1';`
346			`end if;`
347			`WHEN stop_row_calc =>`
348			`stop_idct <= '1';`
349			`result_out <= '1';`
350			`WHEN wait_output_free =>`
351			`--we must wait until next block is capable of receiving data`
352			`WHEN stop_and_start_next_row =>`
353			`--stop calculation of current row, and start next row`
354			`start_idct <= '1';`
355			`stop_idct <= '1';`
356			`result_out <= '1';`
357			`if (col_nr_r /= 6) then`
358			`load_rows <= '1';`
359			`else`
360			`load_columns <= '1';`
361			`end if;`
362			`WHEN OTHERS =>`
363			`NULL;`
364			`END CASE;`
365
366			`END PROCESS csm_output;`
367
368			`----------------------------------------------------------------------------`
369			`csm1_clocked : PROCESS(`
370			`clk,`
371			`rst_n`
372			`)`
373			`----------------------------------------------------------------------------`
374			`BEGIN`
375			`IF (rst_n = '0') THEN`
376			`csm1_current_state <= o_ready;`
377			`-- Reset Values`
378			`wr_out <= '0';`
379			`out_counter_r <= (others => '0');`
380			`ELSIF (clk'EVENT AND clk = '1') THEN`
381			`csm1_current_state <= csm1_next_state;`
382			`-- Registered output assignments`
383			`wr_out <= wr_out_int;`
384
385			`-- Default Assignment To Internals`
386
387			`-- Combined Actions for internal signals only`
388			`CASE csm1_current_state IS`
389			`WHEN o_ready =>`
390			`out_counter_r <= (others => '0');`
391			`WHEN wr_col_to_ram =>`
392			`out_counter_r <= out_counter_r + 1;`
393			`WHEN res_out1 =>`
394			`out_counter_r <= out_counter_r + 1;`
395			`WHEN OTHERS =>`
396			`NULL;`
397			`END CASE;`
398
399			`END IF;`
400
401			`END PROCESS csm1_clocked;`
402
403			`----------------------------------------------------------------------------`
404			`csm1_nextstate : PROCESS (`
405			`csm1_current_state,`
406			`next_block_ready,`
407			`out_counter_r,`
408			`result_out,`
409			`save_result`
410			`)`
411			`----------------------------------------------------------------------------`
412			`BEGIN`
413			`CASE csm1_current_state IS`
414			`WHEN o_ready =>`
415			`IF (save_result = '1') THEN`
416			`csm1_next_state <= result_to_buffer;`
417			`ELSIF (result_out = '1') THEN`
418			`csm1_next_state <= result_to_buffer2;`
419			`ELSE`
420			`csm1_next_state <= o_ready;`
421			`END IF;`
422			`WHEN wr_col_to_ram =>`
423			`IF (out_counter_r = 7) THEN`
424			`csm1_next_state <= o_ready;`
425			`ELSE`
426			`csm1_next_state <= wr_col_to_ram;`
427			`END IF;`
428			`WHEN result_to_buffer =>`
429			`csm1_next_state <= wr_col_to_ram;`
430			`WHEN result_to_buffer2 =>`
431			`IF (next_block_ready = '1') THEN`
432			`csm1_next_state <= res_out1;`
433			`ELSE`
434			`csm1_next_state <= wait_output;`
435			`END IF;`
436			`WHEN res_out1 =>`
437			`IF (out_counter_r = 7) THEN`
438			`csm1_next_state <= o_ready;`
439			`ELSE`
440			`csm1_next_state <= res_out1;`
441			`END IF;`
442			`WHEN wait_output =>`
443			`IF (next_block_ready = '1') THEN`
444			`csm1_next_state <= res_out1;`
445			`ELSE`
446			`csm1_next_state <= wait_output;`
447			`END IF;`
448			`WHEN OTHERS =>`
449			`csm1_next_state <= o_ready;`
450			`END CASE;`
451
452			`END PROCESS csm1_nextstate;`
453
454			`----------------------------------------------------------------------------`
455			`csm1_output : PROCESS (`
456			`csm1_current_state`
457			`)`
458			`----------------------------------------------------------------------------`
459			`BEGIN`
460			`-- Default Assignment`
461			`load_output <= '0';`
462			`out_clk_en <= '0';`
463			`we <= '0';`
464			`wr_out_int <= '0';`
465			`-- Default Assignment To Internals`
466			`output_ready <= '0';`
467
468			`-- Combined Actions`
469			`CASE csm1_current_state IS`
470			`WHEN o_ready =>`
471			`output_ready <= '1';`
472			`WHEN wr_col_to_ram =>`
473			`we <= '1';`
474			`out_clk_en <= '1';`
475			`WHEN result_to_buffer =>`
476			`load_output <= '1';`
477			`WHEN result_to_buffer2 =>`
478			`load_output <= '1';`
479			`WHEN res_out1 =>`
480			`out_clk_en <= '1';`
481			`wr_out_int <= '1';`
482			`--if (col_nr_r = 1 AND out_counter_r = 0) then`
483			`--DC <= '1';`
484			`--end if;`
485			`WHEN OTHERS =>`
486			`NULL;`
487			`END CASE;`
488
489			`END PROCESS csm1_output;`
490
491			`----------------------------------------------------------------------------`
492			`csm2_clocked : PROCESS(`
493			`clk,`
494			`rst_n`
495			`)`
496			`----------------------------------------------------------------------------`
497			`BEGIN`
498			`IF (rst_n = '0') THEN`
499			`csm2_current_state <= i_ready;`
500			`-- Reset Values`
501			`in_counter_r <= (others => '0');`
502			`ELSIF (clk'EVENT AND clk = '1') THEN`
503			`csm2_current_state <= csm2_next_state;`
504			`-- Default Assignment To Internals`
505
506			`-- Combined Actions for internal signals only`
507			`CASE csm2_current_state IS`
508			`WHEN i_ready =>`
509			`in_counter_r <= (OTHERS => '0');`
510			`WHEN i_load_row =>`
511			`in_counter_r <= in_counter_r + 1;`
512			`WHEN i_load_column =>`
513			`if (wr_new_data = '1') then`
514			`in_counter_r <= in_counter_r + 1;`
515			`end if;`
516			`WHEN wait_ram_rd =>`
517			`in_counter_r <= in_counter_r + 1;`
518			`WHEN wait_1st_column =>`
519			`if (wr_new_data = '1') then`
520			`in_counter_r <= in_counter_r + 1;`
521			`end if;`
522			`WHEN OTHERS =>`
523			`NULL;`
524			`END CASE;`
525
526			`END IF;`
527
528			`END PROCESS csm2_clocked;`
529
530			`----------------------------------------------------------------------------`
531			`csm2_nextstate : PROCESS (`
532			`csm2_current_state,`
533			`in_counter_r,`
534			`load_columns,`
535			`load_rows,`
536			`wr_new_data`
537			`)`
538			`----------------------------------------------------------------------------`
539			`BEGIN`
540			`CASE csm2_current_state IS`
541			`WHEN i_ready =>`
542			`IF (load_columns = '1') THEN`
543			`csm2_next_state <= wait_1st_column;`
544			`ELSIF (load_rows = '1') THEN`
545			`csm2_next_state <= wait_ram_rd;`
546			`ELSE`
547			`csm2_next_state <= i_ready;`
548			`END IF;`
549			`WHEN i_load_row =>`
550			`IF (in_counter_r = 7) THEN`
551			`csm2_next_state <= wait_load;`
552			`ELSE`
553			`csm2_next_state <= i_load_row;`
554			`END IF;`
555			`WHEN i_load_column =>`
556			`IF (in_counter_r = 7 AND wr_new_data = '1') THEN`
557			`csm2_next_state <= i_ready;`
558			`ELSE`
559			`csm2_next_state <= i_load_column;`
560			`END IF;`
561			`WHEN wait_ram_rd =>`
562			`csm2_next_state <= i_load_row;`
563			`WHEN wait_load =>`
564			`csm2_next_state <= i_ready;`
565			`WHEN wait_1st_column =>`
566			`IF (wr_new_data = '1') THEN`
567			`csm2_next_state <= i_load_column;`
568			`ELSE`
569			`csm2_next_state <= wait_1st_column;`
570			`END IF;`
571			`WHEN OTHERS =>`
572			`csm2_next_state <= i_ready;`
573			`END CASE;`
574
575			`END PROCESS csm2_nextstate;`
576
577			`----------------------------------------------------------------------------`
578			`csm2_output : PROCESS (`
579			`csm2_current_state,`
580			`wr_new_data`
581			`)`
582			`----------------------------------------------------------------------------`
583			`BEGIN`
584			`-- Default Assignment`
585			`load_input <= '0';`
586			`ready_for_rx <= '0';`
587			`sel_input <= '0';`
588			`-- Default Assignment To Internals`
589			`col_ready <= '0';`
590
591			`-- Combined Actions`
592			`CASE csm2_current_state IS`
593			`WHEN i_ready =>`
594			`col_ready <= '1';`
595			`WHEN i_load_row =>`
596			`sel_input <= '0'; -- load data from ram`
597			`load_input <= '1';`
598			`WHEN i_load_column =>`
599			`sel_input <= '1';`
600			`if (wr_new_data = '1') then`
601			`load_input <= '1';`
602			`end if;`
603			`WHEN wait_ram_rd =>`
604			`sel_input <= '0';`
605			`WHEN wait_load =>`
606			`sel_input <= '0';`
607			`load_input <= '1';`
608			`WHEN wait_1st_column =>`
609			`sel_input <= '1';`
610			`ready_for_rx <= '1';`
611			`if (wr_new_data = '1') then`
612			`load_input <= '1';`
613			`end if;`
614			`WHEN OTHERS =>`
615			`NULL;`
616			`END CASE;`
617
618			`END PROCESS csm2_output;`
619
620			`-- Concurrent Statements`
621			`wraddr <= conv_std_logic_vector(row_wr_nr_r & out_counter_r, 6);`
622			`rdaddr <= conv_std_logic_vector(in_counter_r & row_rd_nr_r, 6);`
623
624			`END fsm;`