| 1 |
145 |
lanttu |
------------------------------------------------------------------------------
|
| 2 |
|
|
-- Author : Timo Alho
|
| 3 |
|
|
-- e-mail : timo.a.alho@tut.fi
|
| 4 |
|
|
-- Date : 21.06.2004 11:30:18
|
| 5 |
|
|
-- File : Rom_idct_even.vhd
|
| 6 |
|
|
-- Design : VHDL Entity Rom_idct_even.rtl
|
| 7 |
|
|
------------------------------------------------------------------------------
|
| 8 |
|
|
-- Description : Pre-calculated 1D-IDCT coefficients for even-half of idct
|
| 9 |
|
|
-- kernel
|
| 10 |
|
|
------------------------------------------------------------------------------
|
| 11 |
|
|
LIBRARY ieee;
|
| 12 |
|
|
USE ieee.std_logic_1164.ALL;
|
| 13 |
|
|
USE ieee.std_logic_arith.ALL;
|
| 14 |
|
|
|
| 15 |
|
|
ENTITY Rom_idct_even IS
|
| 16 |
|
|
GENERIC(
|
| 17 |
|
|
coeffw_g : integer := 14
|
| 18 |
|
|
);
|
| 19 |
|
|
PORT(
|
| 20 |
|
|
addr_in : IN std_logic_vector (3 DOWNTO 0);
|
| 21 |
|
|
clk : IN std_logic;
|
| 22 |
|
|
data_out : OUT std_logic_vector (4*coeffw_g-1 DOWNTO 0)
|
| 23 |
|
|
);
|
| 24 |
|
|
|
| 25 |
|
|
-- Declarations
|
| 26 |
|
|
|
| 27 |
|
|
END Rom_idct_even ;
|
| 28 |
|
|
|
| 29 |
|
|
--
|
| 30 |
|
|
ARCHITECTURE rtl OF Rom_idct_even IS
|
| 31 |
|
|
TYPE Rom16x4x15 IS ARRAY (0 TO 15) OF signed(15*4-1 DOWNTO 0);
|
| 32 |
|
|
CONSTANT ROM_IDCT_EVEN : Rom16x4x15 := (
|
| 33 |
|
|
conv_signed(0, 15) & conv_signed(0, 15) & conv_signed(0, 15) & conv_signed(0, 15),
|
| 34 |
|
|
conv_signed(5681, 15) & conv_signed(4816, 15) & conv_signed(3218, 15) & conv_signed(1130, 15),
|
| 35 |
|
|
conv_signed(4816, 15) & conv_signed(-1130, 15) & conv_signed(-5681, 15) & conv_signed(-3218, 15),
|
| 36 |
|
|
conv_signed(10498, 15) & conv_signed(3686, 15) & conv_signed(-2463, 15) & conv_signed(-2088, 15),
|
| 37 |
|
|
conv_signed(3218, 15) & conv_signed(-5681, 15) & conv_signed(1130, 15) & conv_signed(4816, 15),
|
| 38 |
|
|
conv_signed(8900, 15) & conv_signed(-865, 15) & conv_signed(4348, 15) & conv_signed(5946, 15),
|
| 39 |
|
|
conv_signed(8035, 15) & conv_signed(-6811, 15) & conv_signed(-4551, 15) & conv_signed(1598, 15),
|
| 40 |
|
|
conv_signed(13716, 15) & conv_signed(-1995, 15) & conv_signed(-1333, 15) & conv_signed(2728, 15),
|
| 41 |
|
|
conv_signed(1130, 15) & conv_signed(-3218, 15) & conv_signed(4816, 15) & conv_signed(-5681, 15),
|
| 42 |
|
|
conv_signed(6811, 15) & conv_signed(1598, 15) & conv_signed(8035, 15) & conv_signed(-4551, 15),
|
| 43 |
|
|
conv_signed(5946, 15) & conv_signed(-4348, 15) & conv_signed(-865, 15) & conv_signed(-8900, 15),
|
| 44 |
|
|
conv_signed(11628, 15) & conv_signed(468, 15) & conv_signed(2353, 15) & conv_signed(-7769, 15),
|
| 45 |
|
|
conv_signed(4348, 15) & conv_signed(-8900, 15) & conv_signed(5946, 15) & conv_signed(-865, 15),
|
| 46 |
|
|
conv_signed(10030, 15) & conv_signed(-4083, 15) & conv_signed(9165, 15) & conv_signed(265, 15),
|
| 47 |
|
|
conv_signed(9165, 15) & conv_signed(-10030, 15) & conv_signed(265, 15) & conv_signed(-4083, 15),
|
| 48 |
|
|
conv_signed(14846, 15) & conv_signed(-5213, 15) & conv_signed(3483, 15) & conv_signed(-2953, 15));
|
| 49 |
|
|
|
| 50 |
|
|
SIGNAL addr_r : std_logic_vector(3 DOWNTO 0);
|
| 51 |
|
|
BEGIN
|
| 52 |
|
|
|
| 53 |
|
|
clocked : PROCESS (clk)
|
| 54 |
|
|
BEGIN -- PROCESS clocked
|
| 55 |
|
|
IF clk'event AND clk = '1' THEN -- rising clock edge
|
| 56 |
|
|
addr_r <= addr_in;
|
| 57 |
|
|
END IF;
|
| 58 |
|
|
END PROCESS clocked;
|
| 59 |
|
|
|
| 60 |
|
|
access_rom : PROCESS (addr_r)
|
| 61 |
|
|
VARIABLE address : integer;
|
| 62 |
|
|
BEGIN
|
| 63 |
|
|
address := conv_integer(unsigned(addr_r));
|
| 64 |
|
|
data_out <= conv_std_logic_vector(ROM_IDCT_EVEN(address), 4*coeffw_g);
|
| 65 |
|
|
END PROCESS access_rom;
|
| 66 |
|
|
|
| 67 |
|
|
END rtl;
|
| 68 |
|
|
|
