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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html>
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<head>
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<meta http-equiv="Content-Type"content="text/html; charset=utf-8">
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<title>Kactus2 generated documentation for component port_blinker 1.0</title>
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</head>
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<body>
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<h6>This document was generated by Kactus2 on 16.12.2011 16:06:17 by user ege</h6>
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<p>
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<strong>Table of contents</strong><br>
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<a href="#TUT:ip.hwp.accelerator:port_blinker:1.0">1. Component TUT - ip.hwp.accelerator - port_blinker - 1.0</a><br>
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<a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.modelParams">1.1. Model parameters</a><br>
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<a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.kts_params">1.2. Kactus2 attributes</a><br>
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<a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.ports">1.3. Ports</a><br>
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<a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.interfaces">1.4. Bus interfaces</a><br>
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<a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.fileSets">1.5. File sets</a><br>
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<a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.views">1.6. Views</a><br>
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</p>
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<h1><a id="TUT:ip.hwp.accelerator:port_blinker:1.0">1. Component TUT - ip.hwp.accelerator - port_blinker - 1.0</a></h1>
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<p>
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<img src="TUT.ip.hwp.accelerator.port_blinker.1.0.png" alt="TUT - ip.hwp.accelerator - port_blinker - 1.0 preview picture"><br>
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<strong>Description:</strong> Counts up and inverts output when reaching the limit value. Then start over again.<br>
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<strong>IP-Xact file: </strong><a href="../port_blinker.1.0.xml">port_blinker.1.0.xml</a><br>
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</p>
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<h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.modelParams">1.1 Model parameters</a></h2>
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of model parameters defined for the component">
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<tr>
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<th>Name</th>
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<th>Data type</th>
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<th>Default value</th>
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<th>Description</th>
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</tr> <tr>
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<td>SIGNAL_WIDTH</td>
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<td>integer</td>
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<td>32</td>
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<td>In bits</td>
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</tr>
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</table>
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<h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.kts_params">1.2 Kactus2 attributes</a></h2>
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<p>
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<strong> Product hierarchy: </strong>IP<br>
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<strong> Component implementation: </strong>HW<br>
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<strong> Component firmness: </strong>Mutable<br>
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</p>
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<h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.ports">1.3 Ports</a></h2>
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of all ports the component has.">
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<tr>
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<th>Name</th>
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<th>Direction</th>
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<th>Width</th>
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<th>Left bound</th>
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<th>Right bound</th>
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<th>Port type</th>
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<th>Type definition</th>
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<th>Default value</th>
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<th>Description</th>
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</tr> <tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.clk">clk</a></td>
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<td>in</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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<tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.ena_in">ena_in</a></td>
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<td>in</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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<tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.port_out">port_out</a></td>
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<td>out</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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<tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.rst_n">rst_n</a></td>
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<td>in</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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<tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.val_in">val_in</a></td>
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<td>in</td>
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<td>32</td>
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<td>31</td>
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<td>0</td>
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<td>std_logic_vector</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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</table>
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<h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.interfaces">1.4 Bus interfaces</a></h2>
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<h3>1.4.1 clk</h3>
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<p>
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<strong>Interface mode:</strong> slave<br>
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<strong>Ports used in this interface:</strong>
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</p>
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface clk.">
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<tr>
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<th>Name</th>
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<th>Direction</th>
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<th>Width</th>
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<th>Left bound</th>
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<th>Right bound</th>
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<th>Port type</th>
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<th>Type definition</th>
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<th>Default value</th>
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<th>Description</th>
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</tr> <tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.clk">clk</a></td>
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<td>in</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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</table>
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<h3>1.4.2 port_out</h3>
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<p>
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<strong>Interface mode:</strong> master<br>
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<strong>Ports used in this interface:</strong>
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</p>
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface port_out.">
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<tr>
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<th>Name</th>
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<th>Direction</th>
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<th>Width</th>
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<th>Left bound</th>
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<th>Right bound</th>
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<th>Port type</th>
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<th>Type definition</th>
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<th>Default value</th>
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<th>Description</th>
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</tr> <tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.port_out">port_out</a></td>
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<td>out</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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</table>
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<h3>1.4.3 rst_n</h3>
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<p>
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<strong>Interface mode:</strong> slave<br>
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<strong>Ports used in this interface:</strong>
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</p>
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface rst_n.">
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<tr>
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<th>Name</th>
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<th>Direction</th>
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<th>Width</th>
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<th>Left bound</th>
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<th>Right bound</th>
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<th>Port type</th>
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<th>Type definition</th>
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<th>Default value</th>
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<th>Description</th>
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</tr> <tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.rst_n">rst_n</a></td>
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<td>in</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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</table>
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<h3>1.4.4 signal_gen_if</h3>
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<p>
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<strong>Interface mode:</strong> slave<br>
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<strong>Ports used in this interface:</strong>
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</p>
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of ports contained in interface signal_gen_if.">
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<tr>
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<th>Name</th>
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<th>Direction</th>
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<th>Width</th>
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<th>Left bound</th>
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<th>Right bound</th>
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<th>Port type</th>
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<th>Type definition</th>
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<th>Default value</th>
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<th>Description</th>
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</tr> <tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.ena_in">ena_in</a></td>
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<td>in</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>std_logic</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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<tr>
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<td><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.port.val_in">val_in</a></td>
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<td>in</td>
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<td>32</td>
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<td>31</td>
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<td>0</td>
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<td>std_logic_vector</td>
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<td>IEEE.std_logic_1164.all</td>
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<td></td>
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<td></td>
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</tr>
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</table>
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<h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.fileSets">1.5 File sets</a></h2>
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<h3><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.fileSet.hdlSources">1.5.1 hdlSources</a></h3>
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<p>
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<strong>Identifiers:</strong> <br>
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<strong>Default file builders:</strong>
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</p>
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<table frame="box" rules="all"border="1" cellPadding="3" title="The build settings for files in this file set.">
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<tr>
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<th>File type</th>
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<th>Command</th>
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<th>Flags</th>
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<th>Replace default flags</th>
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</tr> <tr>
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<td>vhdlSource</td>
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<td>vcom</td>
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<td>-quiet -check_synthesis</td>
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<td>false</td>
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</tr>
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</table>
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<h4> 1.5.1.1 Files</h4>
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of files contained in this file set.">
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<tr>
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| 259 |
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<th>File name</th>
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<th>Logical name</th>
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| 261 |
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<th>Build command</th>
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| 262 |
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<th>Build flags</th>
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| 263 |
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<th>Specified file types</th>
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| 264 |
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<th>Description</th>
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| 265 |
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</tr> <tr>
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| 266 |
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<td><a href="../src/port_blinker.vhd">port_blinker.vhd</a></td>
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| 267 |
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<td>work</td>
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| 268 |
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<td></td>
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| 269 |
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<td></td>
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| 270 |
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<td>vhdlSource</td>
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| 271 |
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<td></td>
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| 272 |
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</tr>
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| 273 |
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</table>
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| 274 |
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<h3><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.fileSet.documentation">1.5.2 documentation</a></h3>
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| 275 |
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<p>
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| 276 |
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<strong>Description:</strong> Auto-generated HTML documentation of the component<br>
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| 277 |
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<strong>Identifiers:</strong> documentation<br>
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| 278 |
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</p>
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| 279 |
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<h4> 1.5.2.1 Files</h4>
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| 280 |
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<table frame="box" rules="all"border="1" cellPadding="3" title="List of files contained in this file set.">
|
| 281 |
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<tr>
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| 282 |
|
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<th>File name</th>
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| 283 |
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<th>Logical name</th>
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| 284 |
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<th>Build command</th>
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| 285 |
|
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<th>Build flags</th>
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| 286 |
|
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<th>Specified file types</th>
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| 287 |
|
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<th>Description</th>
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| 288 |
|
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</tr> <tr>
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| 289 |
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<td><a href="port_blinker.html">port_blinker.html</a></td>
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| 290 |
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<td></td>
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| 291 |
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<td></td>
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| 292 |
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<td></td>
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| 293 |
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<td>documentation</td>
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| 294 |
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<td></td>
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| 295 |
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</tr>
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| 296 |
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</table>
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| 297 |
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<h2><a id="TUT:ip.hwp.accelerator:port_blinker:1.0.views">1.6 Views</a></h2>
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| 298 |
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<h3>1.6.1 View: rtl</h3>
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| 299 |
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<p>
|
| 300 |
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<strong> Type: </strong>non-hierarchical<br>
|
| 301 |
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<strong> File sets contained in this view: </strong>
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| 302 |
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</p>
|
| 303 |
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<ul>
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| 304 |
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<li><a href="#TUT:ip.hwp.accelerator:port_blinker:1.0.fileSet.hdlSources">hdlSources</a></li>
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| 305 |
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</ul>
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| 306 |
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<p>
|
| 307 |
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<a href="http://validator.w3.org/check?uri=referer">
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| 308 |
|
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<img src="http://www.w3.org/Icons/valid-html401"alt="Valid HTML 4.01 Strict" height="31"width="88">
|
| 309 |
|
|
</a>
|
| 310 |
|
|
</p>
|
| 311 |
|
|
|
| 312 |
|
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</body>
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| 313 |
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</html>
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