URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [port_blinker/] [1.0/] [ip_xact/] [port_blinker.1.0.xml] - Blame information for rev 145

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        TUT
        ip.hwp.accelerator
        port_blinker
        1.0
        
                
                        clk
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                clk
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        port_out
                        
                        
                        
                        false
                        
                                
                                        
                                                gpio
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                port_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        rst_n
                        
                        
                        
                        false
                        
                                
                                        
                                                RESETn
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                rst_n
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        signal_gen_if
                        
                        
                        
                        false
                        
                                
                                        
                                                ENABLE_FROM_GEN
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                ena_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                SIGNAL_FROM_GEN
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                val_in
                                                
                                                        31
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        
                                rtl
                                vhdl::
                                
                                        hdlSources
                                
                        
                
                
                        
                                clk
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                ena_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                port_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                rst_n
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                val_in
                                
                                        in
                                        
                                                31
                                                0
                                        
                                        
                                                
                                                        std_logic_vector
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                
                
                        
                                SIGNAL_WIDTH
                                In bits
                                32
                        
                
        
        
                
                        hdlSources
                        
                                ../vhd/port_blinker.vhd
                                vhdlSource
                                false
                                work
                                
                                        false
                                
                        
                        
                                vhdlSource
                                vcom
                                -quiet -check_synthesis
                                false
                        
                
                
                        documentation
                        Auto-generated HTML documentation of the component
                        documentation
                        
                                ../doc/port_blinker.html
                                documentation
                                false
                                
                                        false
                                
                        
                        
                                ../doc/TUT.ip.hwp.accelerator.port_blinker.1.0.png
                                jpg
                                false
                                
                                        false
                                
                        
                
        
        Counts up and inverts output when reaching the limit value. Then start over again.
        
                
                        
                                IP
                                HW
                                Mutable
                        
                
        


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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [port_blinker/] [1.0/] [ip_xact/] [port_blinker.1.0.xml] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu
2
3
4			`TUT`
5			`ip.hwp.accelerator`
6			`port_blinker`
7			`1.0`
8
9
10			`clk`
11
12
13
14			`false`
15
16
17
18			`CLK`
19
20			`0`
21			`0`
22
23
24
25			`clk`
26
27			`0`
28			`0`
29
30
31
32
33			`8`
34			`little`
35
36
37			`port_out`
38
39
40
41			`false`
42
43
44
45			`gpio`
46
47			`0`
48			`0`
49
50
51
52			`port_out`
53
54			`0`
55			`0`
56
57
58
59
60			`8`
61			`little`
62
63
64			`rst_n`
65
66
67
68			`false`
69
70
71
72			`RESETn`
73
74			`0`
75			`0`
76
77
78
79			`rst_n`
80
81			`0`
82			`0`
83
84
85
86
87			`8`
88			`little`
89
90
91			`signal_gen_if`
92
93
94
95			`false`
96
97
98
99			`ENABLE_FROM_GEN`
100
101			`0`
102			`0`
103
104
105
106			`ena_in`
107
108			`0`
109			`0`
110
111
112
113
114
115			`SIGNAL_FROM_GEN`
116
117			`31`
118			`0`
119
120
121
122			`val_in`
123
124			`31`
125			`0`
126
127
128
129
130			`8`
131			`little`
132
133
134
135
136
137			`rtl`
138			`vhdl::`
139
140			`hdlSources`
141
142
143
144
145
146			`clk`
147
148			`in`
149
150			`0`
151			`0`
152
153
154
155			`std_logic`
156			`IEEE.std_logic_1164.all`
157			`rtl`
158
159
160
161
162
163			`ena_in`
164
165			`in`
166
167			`0`
168			`0`
169
170
171
172			`std_logic`
173			`IEEE.std_logic_1164.all`
174			`rtl`
175
176
177
178
179
180			`port_out`
181
182			`out`
183
184			`0`
185			`0`
186
187
188
189			`std_logic`
190			`IEEE.std_logic_1164.all`
191			`rtl`
192
193
194
195
196
197			`rst_n`
198
199			`in`
200
201			`0`
202			`0`
203
204
205
206			`std_logic`
207			`IEEE.std_logic_1164.all`
208			`rtl`
209
210
211
212
213
214			`val_in`
215
216			`in`
217
218			`31`
219			`0`
220
221
222
223			`std_logic_vector`
224			`IEEE.std_logic_1164.all`
225			`rtl`
226
227
228
229
230
231
232
233			`SIGNAL_WIDTH`
234			`In bits`
235			`32`
236
237
238
239
240
241			`hdlSources`
242
243			`../vhd/port_blinker.vhd`
244			`vhdlSource`
245			`false`
246			`work`
247
248			`false`
249
250
251
252			`vhdlSource`
253			`vcom`
254			`-quiet -check_synthesis`
255			`false`
256
257
258
259			`documentation`
260			`Auto-generated HTML documentation of the component`
261			`documentation`
262
263			`../doc/port_blinker.html`
264			`documentation`
265			`false`
266
267			`false`
268
269
270
271			`../doc/TUT.ip.hwp.accelerator.port_blinker.1.0.png`
272			`jpg`
273			`false`
274
275			`false`
276
277
278
279
280			`Counts up and inverts output when reaching the limit value. Then start over again.`
281
282
283
284			`IP`
285			`HW`
286			`Mutable`
287
288
289
290