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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [port_blinker/] [1.0/] [ip_xact/] [port_blinker.1.0.xml] - Blame information for rev 181

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Line No. Rev Author Line
1 145 lanttu
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        TUT
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        ip.hwp.accelerator
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        port_blinker
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        1.0
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        Counts up and inverts output when reaching the limit value. Then start over again.
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                        clk
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                clk
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                                                        0
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                                                        0
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                        8
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                        little
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                        port_out
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                        false
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                                                gpio
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                                                        0
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                                                        0
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                                                port_out
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                                                        0
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                                                        0
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                        8
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                        little
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                        rst_n
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                        false
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                                                RESETn
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                                                        0
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                                                        0
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                                                rst_n
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                                                        0
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                                                        0
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                        8
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                        little
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                        signal_gen_if
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                        false
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                                                ENABLE_FROM_GEN
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                                                        0
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                                                        0
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                                                ena_in
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                                                        0
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                                                        0
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                                                SIGNAL_FROM_GEN
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                                                        31
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                                                        0
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                                                val_in
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                                                        31
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                                                        0
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                        8
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                        little
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                                rtl
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                                vhdl::
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                                        hdlSources
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                                clk
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                                        in
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        rtl
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                                ena_in
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                                        in
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        rtl
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                                port_out
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                                        out
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        rtl
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                                rst_n
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                                        in
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        rtl
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                                val_in
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                                        in
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        rtl
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                                SIGNAL_WIDTH
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                                In bits
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                                32
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                        hdlSources
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                                ../vhd/port_blinker.vhd
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                                vhdlSource
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                                false
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                                work
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                                vhdlSource
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                                vcom
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                                -quiet -check_synthesis
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                                false
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                        documentation
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                        Auto-generated HTML documentation of the component
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                        documentation
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                                ../doc/port_blinker.html
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                                documentation
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                                false
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                                ../doc/TUT.ip.hwp.accelerator.port_blinker.1.0.png
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                                jpg
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                                false
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                                IP
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                                HW
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                                Mutable
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