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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [sig_gen/] [1.0/] [ip_xact/] [sig_gen.1.0.xml] - Blame information for rev 145

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        TUT
        ip.hwp.accelerator
        sig_gen
        1.0
        
                
                        clk
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                clk
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        rst_n
                        
                        
                        
                        false
                        
                                
                                        
                                                RESETn
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                rst_n
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        signal_gen_if
                        
                        
                        
                        false
                        
                                
                                        
                                                ENABLE_FROM_GEN
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                ena_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                SIGNAL_FROM_GEN
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                sig_out
                                                
                                                        31
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        toggle_in
                        
                        
                        
                        false
                        
                                
                                        
                                                gpio
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                toggle_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        
                                rtl
                                vhdl::
                                
                                        hdlSources
                                
                        
                
                
                        
                                clk
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                ena_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                rst_n
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                sig_out
                                
                                        out
                                        
                                                31
                                                0
                                        
                                        
                                                
                                                        std_logic_vector
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                        
                                toggle_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                        
                
                
                        
                                SIGNAL_VAL
                                Constant value driven to the output
                                50000000
                        
                        
                                SIGNAL_WIDTH
                                In bits
                                32
                        
                
        
        
                
                        hdlSources
                        
                                ../vhd/sig_gen.vhd
                                vhdlSource
                                false
                                work
                                
                                        false
                                
                        
                        
                                vhdlSource
                                vcom
                                -quiet -check_synthesis
                                false
                        
                
        
        Generates a constant value to the output bus and an enable signal that can be toggled.
        
                
                        
                                IP
                                HW
                                Mutable
                        
                
        


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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [sig_gen/] [1.0/] [ip_xact/] [sig_gen.1.0.xml] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu
2
3
4			`TUT`
5			`ip.hwp.accelerator`
6			`sig_gen`
7			`1.0`
8
9
10			`clk`
11
12
13
14			`false`
15
16
17
18			`CLK`
19
20			`0`
21			`0`
22
23
24
25			`clk`
26
27			`0`
28			`0`
29
30
31
32
33			`8`
34			`little`
35
36
37			`rst_n`
38
39
40
41			`false`
42
43
44
45			`RESETn`
46
47			`0`
48			`0`
49
50
51
52			`rst_n`
53
54			`0`
55			`0`
56
57
58
59
60			`8`
61			`little`
62
63
64			`signal_gen_if`
65
66
67
68			`false`
69
70
71
72			`ENABLE_FROM_GEN`
73
74			`0`
75			`0`
76
77
78
79			`ena_out`
80
81			`0`
82			`0`
83
84
85
86
87
88			`SIGNAL_FROM_GEN`
89
90			`31`
91			`0`
92
93
94
95			`sig_out`
96
97			`31`
98			`0`
99
100
101
102
103			`8`
104			`little`
105
106
107			`toggle_in`
108
109
110
111			`false`
112
113
114
115			`gpio`
116
117			`0`
118			`0`
119
120
121
122			`toggle_in`
123
124			`0`
125			`0`
126
127
128
129
130			`8`
131			`little`
132
133
134
135
136
137			`rtl`
138			`vhdl::`
139
140			`hdlSources`
141
142
143
144
145
146			`clk`
147
148			`in`
149
150			`0`
151			`0`
152
153
154
155			`std_logic`
156			`IEEE.std_logic_1164.all`
157			`rtl`
158
159
160
161
162
163			`ena_out`
164
165			`out`
166
167			`0`
168			`0`
169
170
171
172			`std_logic`
173			`IEEE.std_logic_1164.all`
174			`rtl`
175
176
177
178
179
180			`rst_n`
181
182			`in`
183
184			`0`
185			`0`
186
187
188
189			`std_logic`
190			`IEEE.std_logic_1164.all`
191			`rtl`
192
193
194
195
196
197			`sig_out`
198
199			`out`
200
201			`31`
202			`0`
203
204
205
206			`std_logic_vector`
207			`IEEE.std_logic_1164.all`
208			`rtl`
209
210
211
212
213
214			`toggle_in`
215
216			`in`
217
218			`0`
219			`0`
220
221
222
223			`std_logic`
224			`IEEE.std_logic_1164.all`
225			`rtl`
226
227
228
229
230
231
232
233			`SIGNAL_VAL`
234			`Constant value driven to the output`
235			`50000000`
236
237
238			`SIGNAL_WIDTH`
239			`In bits`
240			`32`
241
242
243
244
245
246			`hdlSources`
247
248			`../vhd/sig_gen.vhd`
249			`vhdlSource`
250			`false`
251			`work`
252
253			`false`
254
255
256
257			`vhdlSource`
258			`vcom`
259			`-quiet -check_synthesis`
260			`false`
261
262
263
264			`Generates a constant value to the output bus and an enable signal that can be toggled.`
265
266
267
268			`IP`
269			`HW`
270			`Mutable`
271
272
273
274