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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [ase_mesh1/] [1.0/] [ip_xact/] [ase_mesh1_top4.1.0.xml] - Blame information for rev 145

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Line No. Rev Author Line
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        TUT
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        ip.hwp.communication
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        ase_mesh1_top4
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        1.0
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        Top level for 2x2 32-bit ase_mesh1 NoC.
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                        clock
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                        false
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                                                CLK
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                                                        0
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                                                clk
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                        little
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                        port0
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                        false
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                                                STALL_IN
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                                                        0
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                                                        0
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                                                DATA_OUT
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                        8
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                        little
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                        port1
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                        false
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                                                STALL_IN
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                                                        0
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                                                        0
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                                                stall1_in
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                                                        31
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                                                data1_out
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                                                        1
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                                                        0
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                        8
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                        port2
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                        false
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                                                STALL_IN
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                                                        0
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                                                        0
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                                                stall2_in
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                                                        0
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                                                        0
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                                                DATA_OUT
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                                                        31
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                                                        0
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                                                data2_out
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                                                        31
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                                                        0
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                                                CMD_OUT
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                                                        1
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                                                cmd2_out
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                                                        1
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                                                        0
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                                                STALL_OUT
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                                                        0
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                                                        0
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                                                stall2_out
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                                                data2_in
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                        8
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                        false
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                                                STALL_IN
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                                                        0
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                                                DATA_OUT
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                                                        31
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                        reset
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                                VHDL::
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                                        DependedHDL
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                                        HDLSource
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                                clk
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                                        in
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                                                        IEEE.std_logic_1164.all
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                                        in
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                                                        IEEE.std_logic_1164.all
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                                        out
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                                                        IEEE.std_logic_1164.all
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                                        in
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                        out
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                cmd2_in
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                                        in
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                cmd2_out
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                                        out
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                                cmd3_in
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                                        in
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                cmd3_out
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                                        out
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data0_in
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                                        in
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                                                31
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data0_out
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                                        out
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data1_in
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                                        in
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data1_out
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                                        out
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data2_in
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                                        in
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data2_out
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                                        out
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data3_in
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                                        in
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                                                31
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data3_out
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                                        out
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                rst_n
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                                        in
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                stall0_in
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                stall0_out
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                                        out
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                stall1_in
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                                        in
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                stall1_out
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                                        out
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                stall2_in
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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901
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                                stall2_out
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                                        out
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                stall3_in
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919 
                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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927
928
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931 
                                stall3_out
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                                        out
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935 
                                                0
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                                                0
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938
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940 
                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                        HDLSource
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                        sourceFiles
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                                ../vhd/ase_mesh1_router.vhd
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                                vhdlSource
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                                false
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                                work
959 
                                Router has connections to 4 neighbors and to IP. Neighbors are are named as compass points: north, east, south and west. Routing is fixed to YX routing and arbitration has fixed priorities among the input ports. Addresses are expressed as number of hops, e.g. 2 up and then 3 to the right.
960 
--              Flow control needs 2 bits downstream (da+av) and 1 upstream (stall)
961
962
963 
                                ../vhd/ase_mesh1.vhd
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                                vhdlSource
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                                false
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                                work
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                                Instantiate variable-sized network from rows*cols routers
968
969
970
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                                ../vhd/ase_mesh1_pkt_codec.vhd
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                                vhdlSource
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                                false
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                                work
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                                Combines the mesh network with packetizers.
976
977
978 
                                ../vhd/ase_mesh1_top4.vhd
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                                vhdlSource
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                                false
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                                work
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                                Creates a fixed size mesh (incl. packetizers)
983
984
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                                vhdlSource
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                                vcom
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                                -quiet -check_synthesis
988 
                                false
989
990
991
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                        DependedHDL
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                                ../../../pkt_codec_mk2/1.0/vhd/log2_pkg.vhd
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                                vhdlSource
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                                false
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                                work
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                                ../../../pkt_codec_mk2/1.0/vhd/ase_noc_pkg.vhd
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                                vhdlSource
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                                false
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                                work
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1005
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                                ../../../pkt_codec_mk2/1.0/vhd/ase_dring1_pkg.vhd
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                                vhdlSource
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                                false
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                                work
1010
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                                ../../../pkt_codec_mk2/1.0/vhd/ase_mesh1_pkg.vhd
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                                vhdlSource
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                                false
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                                work
1016
1017
1018 
                                ../../../../ip.hwp.storage/fifos/fifo_mk2/1.0/vhd/ram_1clk.vhd
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                                vhdlSource
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                                false
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                                work
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1023
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                                ../../../../ip.hwp.storage/fifos/fifo_mk2/1.0/vhd/fifo_2clk.vhd
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                                vhdlSource
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                                false
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                                work
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                                ../../../pkt_codec_mk2/1.0/vhd/addr_gen.vhd
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                                vhdlSource
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                                false
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                                work
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                                ../../../pkt_codec_mk2/1.0/vhd/address_lut.vhd
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                                vhdlSource
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                                false
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                                work
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                                ../../../pkt_codec_mk2/1.0/vhd/addr_rip.vhd
1043 
                                vhdlSource
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                                false
1045 
                                work
1046 
                                Converts the addresses received from NoC to IP. All transfers start with NoC address which can be optionally followed by (memory-mapped original) address.
1047 
This unit rips (removed) the NoC address flit, if wanted. Moreover, this can replace the network address with original address (2nd flit). Or this doesn't  do a thing but just forwards everything to IP.
1048
1049
1050 
                                ../../../pkt_codec_mk2/1.0/vhd/addr_translation.vhd
1051 
                                vhdlSource
1052 
                                false
1053 
                                work
1054
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1056 
                                ../../../pkt_codec_mk2/1.0/vhd/cdc.vhd
1057 
                                vhdlSource
1058 
                                false
1059 
                                work
1060
1061
1062 
                                ../../../pkt_codec_mk2/1.0/vhd/pkt_codec_mk2.vhd
1063 
                                vhdlSource
1064 
                                false
1065 
                                work
1066
1067
1068 
                                vhdlSource
1069 
                                vcom
1070 
                                -quiet -check_synthesis
1071 
                                false
1072
1073
1074
1075
1076
1077
1078 
                                IP
1079 
                                HW
1080 
                                Fixed
1081
1082
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