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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [avalon_to_hibi/] [1.0/] [verilog/] [avalon_to_hibi.v] - Blame information for rev 145

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///////////////////////////////////////////////////////////////////////////////
// Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE.  See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
///////////////////////////////////////////////////////////////////////////////
// **************************************************************************
// File             : avalon_to_hibi.v
// Authors          : Juha Arvio
// Date             : 11.05.2010
// Decription       : Avalon to HIBI
// Version          : 0.2
// Version history  : 21.03.2010   jua   Original version
// **************************************************************************
 
module avalon_to_hibi (
  rst_n,
  clk,
 
  av_wr_data_in,
  av_rd_data_out,
  av_addr_in,
  av_we_in,
  av_re_in,
  av_byte_en_in,
  av_wait_req_out,
 
  hibi_comm_in,
  hibi_data_in,
  hibi_av_in,
  hibi_full_in,
  hibi_one_p_in,
  hibi_empty_in,
  hibi_one_d_in,
 
  hibi_comm_out,
  hibi_data_out,
  hibi_av_out,
  hibi_we_out,
  hibi_re_out );
 
parameter AV_ADDR_SIZE = 19;
 
input rst_n;
input clk;
 
input [31:0] av_wr_data_in;
output [31:0] av_rd_data_out;
input [AV_ADDR_SIZE-1:0] av_addr_in;
input av_we_in;
input av_re_in;
input [3:0] av_byte_en_in;
output av_wait_req_out;
 
input [2:0] hibi_comm_in;
input [31:0] hibi_data_in;
input hibi_av_in;
input hibi_full_in;
input hibi_one_p_in;
input hibi_empty_in;
input hibi_one_d_in;
 
output [2:0] hibi_comm_out;
output [31:0] hibi_data_out;
output hibi_av_out;
output hibi_we_out;
output hibi_re_out;
 
parameter AV_M2H2_ADDR = 2'h0;
parameter AV_HIBI_COMP_0_ADDR = 2'h1;
parameter AV_HIBI_COMP_1_ADDR = 2'h2;
parameter AV_HIBI_COMP_2_ADDR = 2'h3;
 
parameter HIBI_BASE_ADDR = 8'h03;
parameter HIBI_M2H2_BASE_ADDR = 8'h07;
parameter HIBI_M2H2_WRCONF_ADDR = 24'h000200; //24'h000010;
parameter HIBI_M2H2_RDCONF_ADDR = 24'h000100;
parameter HIBI_COMP_0_BASE_ADDR = 8'h05;
parameter HIBI_COMP_1_BASE_ADDR = 8'h15;
parameter HIBI_COMP_2_BASE_ADDR = 8'h29;
 
localparam HIBI_CMD_IDLE       = 3'b000;
localparam HIBI_CMD_WR_CONF    = 3'b001;
localparam HIBI_CMD_WR         = 3'b010;
localparam HIBI_CMD_WR_MSG     = 3'b011;
localparam HIBI_CMD_RD         = 3'b100;
localparam HIBI_CMD_RD_CONF    = 3'b101;
localparam HIBI_CMD_MCAST_DATA = 3'b110;
localparam HIBI_CMD_MCAST_MSG  = 3'b111;
 
localparam WAIT_AV        = 3'h0;
localparam DELAY          = 3'h1;
localparam HIBI_SINGLE_WR = 3'h2;
localparam HIBI_SINGLE_RD = 3'h3;
localparam HIBI_EMPTY_WR  = 3'h4;
localparam M2H2_SINGLE_WR = 3'h5;
localparam M2H2_SINGLE_RD = 3'h6;
 
wire [31:0] av_wr_data;
reg [31:0] av_rd_data;
wire [30:0] av_addr;
wire av_we;
wire av_re;
wire [3:0] av_byte_en;
reg av_wait_req;
 
reg hibi_rd_req;
reg hibi_wr_req;
reg hibi_rd_fifo_ready;
reg hibi_wr_fifo_ready;
 
 
wire hibi_we;
reg hibi_wr_av;
reg [2:0] hibi_wr_comm;
reg [31:0] hibi_wr_data;
 
wire hibi_re;
wire hibi_rd_av;
reg hibi_rd_av_prev;
wire [2:0] hibi_rd_comm;
reg [2:0] hibi_rd_comm_prev;
wire [31:0] hibi_rd_data;
reg [31:0] hibi_rd_data_prev;
 
reg [7:0] hibi_rd_operation_index;
 
reg [2:0] fsm_state;
reg [2:0] sub_state;
 
assign av_wr_data = av_wr_data_in;
assign av_rd_data_out = av_rd_data;
assign av_addr = av_addr_in;
assign av_we = av_we_in;
assign av_re = av_re_in;
assign av_byte_en = av_byte_en_in;
assign av_wait_req_out = av_wait_req & (av_we | av_re);
 
 
 
assign hibi_re = hibi_rd_fifo_ready & hibi_rd_req;
assign hibi_re_out = hibi_re;
 
assign hibi_we = hibi_wr_fifo_ready & hibi_wr_req;
assign hibi_we_out = hibi_we;
 
 
assign hibi_av_out = hibi_wr_av;
assign hibi_comm_out = hibi_wr_comm;
 
assign hibi_data_out = hibi_wr_data;
 
assign hibi_rd_av = hibi_av_in;
assign hibi_rd_comm = hibi_comm_in;
assign hibi_rd_data = hibi_data_in;
 
always@(posedge clk or negedge rst_n)
begin
  if (!rst_n)
  begin
    hibi_rd_fifo_ready <= 0;
  end
  else
  begin
    if (hibi_one_d_in == 1)
    begin
      if (hibi_re == 1) // last read fifo data word was read
      begin
        hibi_rd_fifo_ready <= 0;
      end
      else
      begin
        hibi_rd_fifo_ready <= 1;
      end
    end
    else if (hibi_empty_in == 0) // hibi read fifo has atleast two data words
    begin
      hibi_rd_fifo_ready <= 1;
    end
 
    if (hibi_re)
    begin
      hibi_rd_av_prev <= hibi_rd_av;
      hibi_rd_comm_prev <= hibi_rd_comm;
      hibi_rd_data_prev <= hibi_rd_data;
    end
  end
end
 
always@(posedge clk or negedge rst_n)
begin
  if (!rst_n)
  begin
    hibi_wr_fifo_ready <= 0;
  end
  else
  begin
    if (hibi_one_p_in)
    begin
      if (hibi_we)
      begin
        hibi_wr_fifo_ready <= 0;
      end
      else
      begin
        hibi_wr_fifo_ready <= 1;
      end
    end
    else if (!hibi_full_in)
    begin
      hibi_wr_fifo_ready <= 1;
    end
    else
    begin
      hibi_wr_fifo_ready <= 0;
    end
 
 
  end
 
 
end
 
always@(posedge clk or negedge rst_n)
begin
  if (!rst_n)
  begin
    fsm_state <= WAIT_AV;
    sub_state <= 2'h0;
 
    av_rd_data <= 32'h0;
    av_wait_req <= 1'b0;
 
    hibi_wr_req <= 1'b0;
    hibi_wr_av <= 1'b0;
    hibi_wr_comm <= 3'h0;
    hibi_wr_data <= 32'h0;
    hibi_rd_req <= 1'b0;
 
    hibi_rd_operation_index <= 8'h0;
  end
  else
  begin
    case (fsm_state)
      WAIT_AV:
      begin
        if (av_addr[AV_ADDR_SIZE-1:AV_ADDR_SIZE-2] == AV_M2H2_ADDR) begin
          if (av_we) begin
            fsm_state <= M2H2_SINGLE_WR;
            hibi_wr_req <= 1'b1;
            hibi_wr_av <= 1'b1;
            hibi_wr_comm <= HIBI_CMD_WR;
            hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, HIBI_M2H2_WRCONF_ADDR};
          end
          else if (av_re) begin
            fsm_state <= M2H2_SINGLE_RD;
            hibi_wr_req <= 1'b1;
            hibi_wr_av <= 1'b1;
            hibi_wr_comm <= HIBI_CMD_WR; //HIBI_CMD_RD;
            hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, HIBI_M2H2_RDCONF_ADDR};
          end
        end
 
        else begin // if (av_addr[AV_ADDR_SIZE-1:AV_ADDR_SIZE-2] >= AV_HIBI_COMP_0_ADDR) begin
          case (av_addr[AV_ADDR_SIZE-1:AV_ADDR_SIZE-2])
            AV_HIBI_COMP_0_ADDR:
            begin
              hibi_wr_data <= {HIBI_COMP_0_BASE_ADDR, {(24 - AV_ADDR_SIZE){1'b0}}, av_addr[AV_ADDR_SIZE-3:0], 2'b00};
            end
            AV_HIBI_COMP_1_ADDR:
            begin
              hibi_wr_data <= {HIBI_COMP_1_BASE_ADDR, {(24 - AV_ADDR_SIZE){1'b0}}, av_addr[AV_ADDR_SIZE-3:0], 2'b00};
            end
            AV_HIBI_COMP_2_ADDR:
            begin
              hibi_wr_data <= {HIBI_COMP_2_BASE_ADDR, {(24 - AV_ADDR_SIZE){1'b0}}, av_addr[AV_ADDR_SIZE-3:0], 2'b00};
            end
          endcase
 
          if (av_we) begin
            if (av_byte_en == 4'h0) begin
              fsm_state <= HIBI_EMPTY_WR;
            end
            else begin
              fsm_state <= HIBI_SINGLE_WR;
              hibi_wr_req <= 1'b1;
            end
 
            hibi_wr_av <= 1'b1;
            hibi_wr_comm <= HIBI_CMD_WR;
          end
          else if (av_re) begin
            fsm_state <= HIBI_SINGLE_RD;
            hibi_wr_req <= 1'b1;
            hibi_wr_av <= 1'b1;
            hibi_wr_comm <= HIBI_CMD_RD;
          end
        end
 
        sub_state <= 2'h0;
        av_wait_req <= 1'b1;
      end
      DELAY:
      begin
        av_wait_req <= 1'b1;
        fsm_state <= WAIT_AV;
      end
      HIBI_SINGLE_WR:
      begin
        if (hibi_we) begin
          case (sub_state)
            3'h0:
            begin
              hibi_wr_av <= 1'b0;
              hibi_wr_data <= av_wr_data;
            end
            default: //3'h1:
            begin
              hibi_wr_req <= 1'b0;
 
 
              fsm_state <= DELAY;
              av_wait_req <= 1'b0;
            end
          endcase
 
          sub_state <= sub_state + 1;
        end
      end
      HIBI_SINGLE_RD:
      begin
        if (hibi_we || hibi_re) begin
          sub_state <= sub_state + 1;
 
          case (sub_state)
            3'h0:
            begin
              hibi_wr_av <= 1'b0;
              hibi_wr_data <= {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index};
            end
            3'h1:
            begin
              hibi_wr_req <= 1'b0;
              hibi_rd_req <= 1'b1;
            end
            3'h2:
            begin
              if ( !(hibi_rd_av && (hibi_rd_data == {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index})) ) begin
                sub_state <= sub_state;
              end
            end
            default: //3'h3:
            begin
              av_rd_data <= hibi_rd_data;
 
              fsm_state <= DELAY;
              av_wait_req <= 1'b0;
 
              hibi_rd_operation_index <= hibi_rd_operation_index + 1;
            end
          endcase
        end
      end
      HIBI_EMPTY_WR:
      begin
        fsm_state <= DELAY;
        av_wait_req <= 1'b0;
      end
      M2H2_SINGLE_WR:
      begin
        if (hibi_we || (sub_state == 3'h4)) begin
          case (sub_state)
            3'h0:
            begin
              hibi_wr_av <= 1'b0;
              hibi_wr_data <= {1'h0, av_byte_en, 27'h0000001}; // post_rw_cmd = 0, byte_en = av_byte_en, mem_rw_length = 1
            end
            3'h1:
            begin
              hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, av_addr[23:0]};
            end
            3'h2:
            begin
              hibi_wr_data <= av_wr_data;
            end
            default: //3'h3:
            begin
              hibi_wr_req <= 1'b0;
              av_wait_req <= 1'b0;
              fsm_state <= DELAY;
            end
 
          endcase
 
          sub_state <= sub_state + 1;
        end
      end
      M2H2_SINGLE_RD:
      begin
        if (hibi_we || hibi_re) begin
          sub_state <= sub_state + 1;
 
          case (sub_state)
            3'h0:
            begin
              hibi_wr_av <= 1'b0;
              hibi_wr_data <= 32'h78000001; // post_rw_cmd = 0, byte_en = 0xF, mem_rw_length = 1
            end
            3'h1:
            begin
              hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, av_addr[23:0]};
            end
            3'h2:
            begin
              hibi_wr_data <= {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index};
            end
            3'h3:
            begin
              hibi_wr_req <= 1'b0;
              hibi_rd_req <= 1'b1;
            end
            3'h4:
            begin
              if ( !(hibi_rd_av && (hibi_rd_data == {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index})) ) begin
                sub_state <= sub_state;
              end
            end
            default: //3'h5:
            begin
              av_rd_data <= hibi_rd_data;
 
              fsm_state <= DELAY;
              av_wait_req <= 1'b0;
 
              hibi_rd_operation_index <= hibi_rd_operation_index + 1;
            end
          endcase
        end
      end
    endcase
  end
end
 
 
endmodule

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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [avalon_to_hibi/] [1.0/] [verilog/] [avalon_to_hibi.v] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu	`///////////////////////////////////////////////////////////////////////////////`
2			`// Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems`
3			`//`
4			`// This source file may be used and distributed without`
5			`// restriction provided that this copyright statement is not`
6			`// removed from the file and that any derivative work contains`
7			`// the original copyright notice and the associated disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it`
10			`// and/or modify it under the terms of the GNU Lesser General`
11			`// Public License as published by the Free Software Foundation;`
12			`// either version 2.1 of the License, or (at your option) any`
13			`// later version.`
14			`//`
15			`// This source is distributed in the hope that it will be`
16			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
17			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
18			`// PURPOSE. See the GNU Lesser General Public License for more`
19			`// details.`
20			`//`
21			`// You should have received a copy of the GNU Lesser General`
22			`// Public License along with this source; if not, download it`
23			`// from http://www.opencores.org/lgpl.shtml`
24			`///////////////////////////////////////////////////////////////////////////////`
25			`// **************************************************************************`
26			`// File : avalon_to_hibi.v`
27			`// Authors : Juha Arvio`
28			`// Date : 11.05.2010`
29			`// Decription : Avalon to HIBI`
30			`// Version : 0.2`
31			`// Version history : 21.03.2010 jua Original version`
32			`// **************************************************************************`
33
34			`module avalon_to_hibi (`
35			`rst_n,`
36			`clk,`
37
38			`av_wr_data_in,`
39			`av_rd_data_out,`
40			`av_addr_in,`
41			`av_we_in,`
42			`av_re_in,`
43			`av_byte_en_in,`
44			`av_wait_req_out,`
45
46			`hibi_comm_in,`
47			`hibi_data_in,`
48			`hibi_av_in,`
49			`hibi_full_in,`
50			`hibi_one_p_in,`
51			`hibi_empty_in,`
52			`hibi_one_d_in,`
53
54			`hibi_comm_out,`
55			`hibi_data_out,`
56			`hibi_av_out,`
57			`hibi_we_out,`
58			`hibi_re_out );`
59
60			`parameter AV_ADDR_SIZE = 19;`
61
62			`input rst_n;`
63			`input clk;`
64
65			`input [31:0] av_wr_data_in;`
66			`output [31:0] av_rd_data_out;`
67			`input [AV_ADDR_SIZE-1:0] av_addr_in;`
68			`input av_we_in;`
69			`input av_re_in;`
70			`input [3:0] av_byte_en_in;`
71			`output av_wait_req_out;`
72
73			`input [2:0] hibi_comm_in;`
74			`input [31:0] hibi_data_in;`
75			`input hibi_av_in;`
76			`input hibi_full_in;`
77			`input hibi_one_p_in;`
78			`input hibi_empty_in;`
79			`input hibi_one_d_in;`
80
81			`output [2:0] hibi_comm_out;`
82			`output [31:0] hibi_data_out;`
83			`output hibi_av_out;`
84			`output hibi_we_out;`
85			`output hibi_re_out;`
86
87			`parameter AV_M2H2_ADDR = 2'h0;`
88			`parameter AV_HIBI_COMP_0_ADDR = 2'h1;`
89			`parameter AV_HIBI_COMP_1_ADDR = 2'h2;`
90			`parameter AV_HIBI_COMP_2_ADDR = 2'h3;`
91
92			`parameter HIBI_BASE_ADDR = 8'h03;`
93			`parameter HIBI_M2H2_BASE_ADDR = 8'h07;`
94			`parameter HIBI_M2H2_WRCONF_ADDR = 24'h000200; //24'h000010;`
95			`parameter HIBI_M2H2_RDCONF_ADDR = 24'h000100;`
96			`parameter HIBI_COMP_0_BASE_ADDR = 8'h05;`
97			`parameter HIBI_COMP_1_BASE_ADDR = 8'h15;`
98			`parameter HIBI_COMP_2_BASE_ADDR = 8'h29;`
99
100			`localparam HIBI_CMD_IDLE = 3'b000;`
101			`localparam HIBI_CMD_WR_CONF = 3'b001;`
102			`localparam HIBI_CMD_WR = 3'b010;`
103			`localparam HIBI_CMD_WR_MSG = 3'b011;`
104			`localparam HIBI_CMD_RD = 3'b100;`
105			`localparam HIBI_CMD_RD_CONF = 3'b101;`
106			`localparam HIBI_CMD_MCAST_DATA = 3'b110;`
107			`localparam HIBI_CMD_MCAST_MSG = 3'b111;`
108
109			`localparam WAIT_AV = 3'h0;`
110			`localparam DELAY = 3'h1;`
111			`localparam HIBI_SINGLE_WR = 3'h2;`
112			`localparam HIBI_SINGLE_RD = 3'h3;`
113			`localparam HIBI_EMPTY_WR = 3'h4;`
114			`localparam M2H2_SINGLE_WR = 3'h5;`
115			`localparam M2H2_SINGLE_RD = 3'h6;`
116
117			`wire [31:0] av_wr_data;`
118			`reg [31:0] av_rd_data;`
119			`wire [30:0] av_addr;`
120			`wire av_we;`
121			`wire av_re;`
122			`wire [3:0] av_byte_en;`
123			`reg av_wait_req;`
124
125			`reg hibi_rd_req;`
126			`reg hibi_wr_req;`
127			`reg hibi_rd_fifo_ready;`
128			`reg hibi_wr_fifo_ready;`
129
130
131			`wire hibi_we;`
132			`reg hibi_wr_av;`
133			`reg [2:0] hibi_wr_comm;`
134			`reg [31:0] hibi_wr_data;`
135
136			`wire hibi_re;`
137			`wire hibi_rd_av;`
138			`reg hibi_rd_av_prev;`
139			`wire [2:0] hibi_rd_comm;`
140			`reg [2:0] hibi_rd_comm_prev;`
141			`wire [31:0] hibi_rd_data;`
142			`reg [31:0] hibi_rd_data_prev;`
143
144			`reg [7:0] hibi_rd_operation_index;`
145
146			`reg [2:0] fsm_state;`
147			`reg [2:0] sub_state;`
148
149			`assign av_wr_data = av_wr_data_in;`
150			`assign av_rd_data_out = av_rd_data;`
151			`assign av_addr = av_addr_in;`
152			`assign av_we = av_we_in;`
153			`assign av_re = av_re_in;`
154			`assign av_byte_en = av_byte_en_in;`
155			`assign av_wait_req_out = av_wait_req & (av_we \| av_re);`
156
157
158
159			`assign hibi_re = hibi_rd_fifo_ready & hibi_rd_req;`
160			`assign hibi_re_out = hibi_re;`
161
162			`assign hibi_we = hibi_wr_fifo_ready & hibi_wr_req;`
163			`assign hibi_we_out = hibi_we;`
164
165
166			`assign hibi_av_out = hibi_wr_av;`
167			`assign hibi_comm_out = hibi_wr_comm;`
168
169			`assign hibi_data_out = hibi_wr_data;`
170
171			`assign hibi_rd_av = hibi_av_in;`
172			`assign hibi_rd_comm = hibi_comm_in;`
173			`assign hibi_rd_data = hibi_data_in;`
174
175			`always@(posedge clk or negedge rst_n)`
176			`begin`
177			`if (!rst_n)`
178			`begin`
179			`hibi_rd_fifo_ready <= 0;`
180			`end`
181			`else`
182			`begin`
183			`if (hibi_one_d_in == 1)`
184			`begin`
185			`if (hibi_re == 1) // last read fifo data word was read`
186			`begin`
187			`hibi_rd_fifo_ready <= 0;`
188			`end`
189			`else`
190			`begin`
191			`hibi_rd_fifo_ready <= 1;`
192			`end`
193			`end`
194			`else if (hibi_empty_in == 0) // hibi read fifo has atleast two data words`
195			`begin`
196			`hibi_rd_fifo_ready <= 1;`
197			`end`
198
199			`if (hibi_re)`
200			`begin`
201			`hibi_rd_av_prev <= hibi_rd_av;`
202			`hibi_rd_comm_prev <= hibi_rd_comm;`
203			`hibi_rd_data_prev <= hibi_rd_data;`
204			`end`
205			`end`
206			`end`
207
208			`always@(posedge clk or negedge rst_n)`
209			`begin`
210			`if (!rst_n)`
211			`begin`
212			`hibi_wr_fifo_ready <= 0;`
213			`end`
214			`else`
215			`begin`
216			`if (hibi_one_p_in)`
217			`begin`
218			`if (hibi_we)`
219			`begin`
220			`hibi_wr_fifo_ready <= 0;`
221			`end`
222			`else`
223			`begin`
224			`hibi_wr_fifo_ready <= 1;`
225			`end`
226			`end`
227			`else if (!hibi_full_in)`
228			`begin`
229			`hibi_wr_fifo_ready <= 1;`
230			`end`
231			`else`
232			`begin`
233			`hibi_wr_fifo_ready <= 0;`
234			`end`
235
236
237			`end`
238
239
240			`end`
241
242			`always@(posedge clk or negedge rst_n)`
243			`begin`
244			`if (!rst_n)`
245			`begin`
246			`fsm_state <= WAIT_AV;`
247			`sub_state <= 2'h0;`
248
249			`av_rd_data <= 32'h0;`
250			`av_wait_req <= 1'b0;`
251
252			`hibi_wr_req <= 1'b0;`
253			`hibi_wr_av <= 1'b0;`
254			`hibi_wr_comm <= 3'h0;`
255			`hibi_wr_data <= 32'h0;`
256			`hibi_rd_req <= 1'b0;`
257
258			`hibi_rd_operation_index <= 8'h0;`
259			`end`
260			`else`
261			`begin`
262			`case (fsm_state)`
263			`WAIT_AV:`
264			`begin`
265			`if (av_addr[AV_ADDR_SIZE-1:AV_ADDR_SIZE-2] == AV_M2H2_ADDR) begin`
266			`if (av_we) begin`
267			`fsm_state <= M2H2_SINGLE_WR;`
268			`hibi_wr_req <= 1'b1;`
269			`hibi_wr_av <= 1'b1;`
270			`hibi_wr_comm <= HIBI_CMD_WR;`
271			`hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, HIBI_M2H2_WRCONF_ADDR};`
272			`end`
273			`else if (av_re) begin`
274			`fsm_state <= M2H2_SINGLE_RD;`
275			`hibi_wr_req <= 1'b1;`
276			`hibi_wr_av <= 1'b1;`
277			`hibi_wr_comm <= HIBI_CMD_WR; //HIBI_CMD_RD;`
278			`hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, HIBI_M2H2_RDCONF_ADDR};`
279			`end`
280			`end`
281
282			`else begin // if (av_addr[AV_ADDR_SIZE-1:AV_ADDR_SIZE-2] >= AV_HIBI_COMP_0_ADDR) begin`
283			`case (av_addr[AV_ADDR_SIZE-1:AV_ADDR_SIZE-2])`
284			`AV_HIBI_COMP_0_ADDR:`
285			`begin`
286			`hibi_wr_data <= {HIBI_COMP_0_BASE_ADDR, {(24 - AV_ADDR_SIZE){1'b0}}, av_addr[AV_ADDR_SIZE-3:0], 2'b00};`
287			`end`
288			`AV_HIBI_COMP_1_ADDR:`
289			`begin`
290			`hibi_wr_data <= {HIBI_COMP_1_BASE_ADDR, {(24 - AV_ADDR_SIZE){1'b0}}, av_addr[AV_ADDR_SIZE-3:0], 2'b00};`
291			`end`
292			`AV_HIBI_COMP_2_ADDR:`
293			`begin`
294			`hibi_wr_data <= {HIBI_COMP_2_BASE_ADDR, {(24 - AV_ADDR_SIZE){1'b0}}, av_addr[AV_ADDR_SIZE-3:0], 2'b00};`
295			`end`
296			`endcase`
297
298			`if (av_we) begin`
299			`if (av_byte_en == 4'h0) begin`
300			`fsm_state <= HIBI_EMPTY_WR;`
301			`end`
302			`else begin`
303			`fsm_state <= HIBI_SINGLE_WR;`
304			`hibi_wr_req <= 1'b1;`
305			`end`
306
307			`hibi_wr_av <= 1'b1;`
308			`hibi_wr_comm <= HIBI_CMD_WR;`
309			`end`
310			`else if (av_re) begin`
311			`fsm_state <= HIBI_SINGLE_RD;`
312			`hibi_wr_req <= 1'b1;`
313			`hibi_wr_av <= 1'b1;`
314			`hibi_wr_comm <= HIBI_CMD_RD;`
315			`end`
316			`end`
317
318			`sub_state <= 2'h0;`
319			`av_wait_req <= 1'b1;`
320			`end`
321			`DELAY:`
322			`begin`
323			`av_wait_req <= 1'b1;`
324			`fsm_state <= WAIT_AV;`
325			`end`
326			`HIBI_SINGLE_WR:`
327			`begin`
328			`if (hibi_we) begin`
329			`case (sub_state)`
330			`3'h0:`
331			`begin`
332			`hibi_wr_av <= 1'b0;`
333			`hibi_wr_data <= av_wr_data;`
334			`end`
335			`default: //3'h1:`
336			`begin`
337			`hibi_wr_req <= 1'b0;`
338
339
340			`fsm_state <= DELAY;`
341			`av_wait_req <= 1'b0;`
342			`end`
343			`endcase`
344
345			`sub_state <= sub_state + 1;`
346			`end`
347			`end`
348			`HIBI_SINGLE_RD:`
349			`begin`
350			`if (hibi_we \|\| hibi_re) begin`
351			`sub_state <= sub_state + 1;`
352
353			`case (sub_state)`
354			`3'h0:`
355			`begin`
356			`hibi_wr_av <= 1'b0;`
357			`hibi_wr_data <= {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index};`
358			`end`
359			`3'h1:`
360			`begin`
361			`hibi_wr_req <= 1'b0;`
362			`hibi_rd_req <= 1'b1;`
363			`end`
364			`3'h2:`
365			`begin`
366			`if ( !(hibi_rd_av && (hibi_rd_data == {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index})) ) begin`
367			`sub_state <= sub_state;`
368			`end`
369			`end`
370			`default: //3'h3:`
371			`begin`
372			`av_rd_data <= hibi_rd_data;`
373
374			`fsm_state <= DELAY;`
375			`av_wait_req <= 1'b0;`
376
377			`hibi_rd_operation_index <= hibi_rd_operation_index + 1;`
378			`end`
379			`endcase`
380			`end`
381			`end`
382			`HIBI_EMPTY_WR:`
383			`begin`
384			`fsm_state <= DELAY;`
385			`av_wait_req <= 1'b0;`
386			`end`
387			`M2H2_SINGLE_WR:`
388			`begin`
389			`if (hibi_we \|\| (sub_state == 3'h4)) begin`
390			`case (sub_state)`
391			`3'h0:`
392			`begin`
393			`hibi_wr_av <= 1'b0;`
394			`hibi_wr_data <= {1'h0, av_byte_en, 27'h0000001}; // post_rw_cmd = 0, byte_en = av_byte_en, mem_rw_length = 1`
395			`end`
396			`3'h1:`
397			`begin`
398			`hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, av_addr[23:0]};`
399			`end`
400			`3'h2:`
401			`begin`
402			`hibi_wr_data <= av_wr_data;`
403			`end`
404			`default: //3'h3:`
405			`begin`
406			`hibi_wr_req <= 1'b0;`
407			`av_wait_req <= 1'b0;`
408			`fsm_state <= DELAY;`
409			`end`
410
411			`endcase`
412
413			`sub_state <= sub_state + 1;`
414			`end`
415			`end`
416			`M2H2_SINGLE_RD:`
417			`begin`
418			`if (hibi_we \|\| hibi_re) begin`
419			`sub_state <= sub_state + 1;`
420
421			`case (sub_state)`
422			`3'h0:`
423			`begin`
424			`hibi_wr_av <= 1'b0;`
425			`hibi_wr_data <= 32'h78000001; // post_rw_cmd = 0, byte_en = 0xF, mem_rw_length = 1`
426			`end`
427			`3'h1:`
428			`begin`
429			`hibi_wr_data <= {HIBI_M2H2_BASE_ADDR, av_addr[23:0]};`
430			`end`
431			`3'h2:`
432			`begin`
433			`hibi_wr_data <= {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index};`
434			`end`
435			`3'h3:`
436			`begin`
437			`hibi_wr_req <= 1'b0;`
438			`hibi_rd_req <= 1'b1;`
439			`end`
440			`3'h4:`
441			`begin`
442			`if ( !(hibi_rd_av && (hibi_rd_data == {HIBI_BASE_ADDR, 16'h0, hibi_rd_operation_index})) ) begin`
443			`sub_state <= sub_state;`
444			`end`
445			`end`
446			`default: //3'h5:`
447			`begin`
448			`av_rd_data <= hibi_rd_data;`
449
450			`fsm_state <= DELAY;`
451			`av_wait_req <= 1'b0;`
452
453			`hibi_rd_operation_index <= hibi_rd_operation_index + 1;`
454			`end`
455			`endcase`
456			`end`
457			`end`
458			`endcase`
459			`end`
460			`end`
461
462
463			`endmodule`