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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [basic_tester/] [1.0/] [ip_xact/] [basic_tester_tx.1.0.xml] - Blame information for rev 145

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        TUT
        ip.hwp.communication
        basic_tester_tx
        1.0
        Simple unit for sending test data. There are separate units for transmitting (tx) and receiving (rx). This one sends commands to the tested IP (e.g. via HIBI). The other unit can then check the returned data.
 
This IP-XACT component is fixed to 32-bit data and 5-bit command.
 
Works only in simulation because configuration is done with ASCII file.
        
                
                        clock
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                clk
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        hibi_master
                        Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.
                        
                        
                        
                        false
                        
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                agent_comm_out
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                agent_data_out
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                WE
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                agent_we_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                agent_av_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        hibi_slave
                        
                        
                        
                        false
                        
                                
                                        
                                                ONE_P
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                agent_one_p_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                agent_full_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        reset
                        
                        
                        
                        false
                        
                                
                                        
                                                RESETn
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                rst_n
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        
                                rtl
                                VHDL::
                                
                                        rtl
                                
                        
                
                
                        
                                agent_av_out
                                
                                        out
                                
                                
                        
                        
                                agent_comm_out
                                
                                        out
                                        
                                                4
                                                0
                                        
                                
                                
                        
                        
                                agent_data_out
                                
                                        out
                                        
                                                31
                                                0
                                        
                                
                                
                        
                        
                                agent_full_in
                                
                                        in
                                
                                
                        
                        
                                agent_one_p_in
                                
                                        in
                                
                                
                        
                        
                                agent_we_out
                                
                                        out
                                
                                
                        
                        
                                clk
                                
                                        in
                                
                                
                        
                        
                                done_out
                                
                                        out
                                
                                
                        
                        
                                rst_n
                                Active low
                                
                                        in
                                
                                
                        
                
                
                        
                                comm_width_g
                                5
                        
                        
                                conf_file_g
                                File that contains the sent data
                                test_tx.txt
                        
                        
                                data_width_g
                                32
                        
                
        
        
                
                        rtl
                        VHDL sources
                        
                                ../vhd/txt_util.vhd
                                vhdlSource
                                false
                                work
                                
                                        false
                                
                        
                        
                                ../vhd/basic_tester_pkg.vhd
                                vhdlSource
                                false
                                work
                                
                                        false
                                
                        
                        
                                ../vhd/basic_tester_tx.vhd
                                vhdlSource
                                false
                                work
                                
                                        false
                                
                        
                        
                                vhdlSource
                                vcom
                                -check_synthesis
                                false
                        
                
                
                        example_usage
                        Instantiates tx, rx and 2 hibi wrappers. Tx sends few values. Rx catches them and checks their contents and reception times.
                        
                                ../tb/tb_basic_tester.vhd
                                vhdlSource
                                false
                                work
                                
                                        false
                                
                                Top-level. Generates clock and reset, instantiates basic tester tx+rx and hibi wrappers.
                        
                        
                                ../vhd/basic_tester_rx.vhd
                                vhdlSource
                                false
                                work
                                
                                        false
                                
                                Receiver unit.
                        
                        
                                ../sim/test_tx.txt
                                ASCII
                                false
                                
                                        false
                                
                                Contents of transmitted values
                        
                        
                                ../sim/compile_all.sh
                                shell script
                                false
                                
                                        false
                                
                                
                                Creates VHDL libraries and compiles everything.

                        
                        
                                ../sim/tb_basic_tester.do
                                Modelsim macro
                                false
                                
                                        false
                                
                                Sets up the wave viewer
                        
                        
                                ../sim/test_rx.txt
                                ASCII
                                false
                                
                                        false
                                
                                Expected values for the receiver

                        
                        
                                vhdlSource
                                vcom
                                -check_synthesis
                                false
                        
                        ../../../../ip.hwp.storage/fifos
                        ../../../../ip.hwp.storage/fifos/multi_clk/vhd
                        ../../../hibi/3.0/vhd
                
        
        
                
                        
                                IP
                                HW
                                Fixed
                        
                
        


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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [basic_tester/] [1.0/] [ip_xact/] [basic_tester_tx.1.0.xml] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu
2
3
4			`TUT`
5			`ip.hwp.communication`
6			`basic_tester_tx`
7			`1.0`
8			`Simple unit for sending test data. There are separate units for transmitting (tx) and receiving (rx). This one sends commands to the tested IP (e.g. via HIBI). The other unit can then check the returned data.`
9
10			`This IP-XACT component is fixed to 32-bit data and 5-bit command.`
11
12			`Works only in simulation because configuration is done with ASCII file.`
13
14
15			`clock`
16
17
18
19			`false`
20
21
22
23			`CLK`
24
25			`0`
26			`0`
27
28
29
30			`clk`
31
32			`0`
33			`0`
34
35
36
37
38			`8`
39			`little`
40
41
42			`hibi_master`
43			`Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.`
44
45
46
47			`false`
48
49
50
51			`COMM`
52
53			`4`
54			`0`
55
56
57
58			`agent_comm_out`
59
60			`4`
61			`0`
62
63
64
65
66
67			`DATA`
68
69			`31`
70			`0`
71
72
73
74			`agent_data_out`
75
76			`31`
77			`0`
78
79
80
81
82
83			`WE`
84
85			`0`
86			`0`
87
88
89
90			`agent_we_out`
91
92			`0`
93			`0`
94
95
96
97
98
99			`AV`
100
101			`0`
102			`0`
103
104
105
106			`agent_av_out`
107
108			`0`
109			`0`
110
111
112
113
114			`8`
115			`little`
116
117
118			`hibi_slave`
119
120
121
122			`false`
123
124
125
126			`ONE_P`
127
128			`0`
129			`0`
130
131
132
133			`agent_one_p_in`
134
135			`0`
136			`0`
137
138
139
140
141
142			`FULL`
143
144			`0`
145			`0`
146
147
148
149			`agent_full_in`
150
151			`0`
152			`0`
153
154
155
156
157			`8`
158			`little`
159
160
161			`reset`
162
163
164
165			`false`
166
167
168
169			`RESETn`
170
171			`0`
172			`0`
173
174
175
176			`rst_n`
177
178			`0`
179			`0`
180
181
182
183
184			`8`
185			`little`
186
187
188
189
190
191			`rtl`
192			`VHDL::`
193
194			`rtl`
195
196
197
198
199
200			`agent_av_out`
201
202			`out`
203
204
205
206
207			`agent_comm_out`
208
209			`out`
210
211			`4`
212			`0`
213
214
215
216
217
218			`agent_data_out`
219
220			`out`
221
222			`31`
223			`0`
224
225
226
227
228
229			`agent_full_in`
230
231			`in`
232
233
234
235
236			`agent_one_p_in`
237
238			`in`
239
240
241
242
243			`agent_we_out`
244
245			`out`
246
247
248
249
250			`clk`
251
252			`in`
253
254
255
256
257			`done_out`
258
259			`out`
260
261
262
263
264			`rst_n`
265			`Active low`
266
267			`in`
268
269
270
271
272
273
274			`comm_width_g`
275			`5`
276
277
278			`conf_file_g`
279			`File that contains the sent data`
280			`test_tx.txt`
281
282
283			`data_width_g`
284			`32`
285
286
287
288
289
290			`rtl`
291			`VHDL sources`
292
293			`../vhd/txt_util.vhd`
294			`vhdlSource`
295			`false`
296			`work`
297
298			`false`
299
300
301
302			`../vhd/basic_tester_pkg.vhd`
303			`vhdlSource`
304			`false`
305			`work`
306
307			`false`
308
309
310
311			`../vhd/basic_tester_tx.vhd`
312			`vhdlSource`
313			`false`
314			`work`
315
316			`false`
317
318
319
320			`vhdlSource`
321			`vcom`
322			`-check_synthesis`
323			`false`
324
325
326
327			`example_usage`
328			`Instantiates tx, rx and 2 hibi wrappers. Tx sends few values. Rx catches them and checks their contents and reception times.`
329
330			`../tb/tb_basic_tester.vhd`
331			`vhdlSource`
332			`false`
333			`work`
334
335			`false`
336
337			`Top-level. Generates clock and reset, instantiates basic tester tx+rx and hibi wrappers.`
338
339
340			`../vhd/basic_tester_rx.vhd`
341			`vhdlSource`
342			`false`
343			`work`
344
345			`false`
346
347			`Receiver unit.`
348
349
350			`../sim/test_tx.txt`
351			`ASCII`
352			`false`
353
354			`false`
355
356			`Contents of transmitted values`
357
358
359			`../sim/compile_all.sh`
360			`shell script`
361			`false`
362
363			`false`
364
365
366			`Creates VHDL libraries and compiles everything.`
367
368
369
370			`../sim/tb_basic_tester.do`
371			`Modelsim macro`
372			`false`
373
374			`false`
375
376			`Sets up the wave viewer`
377
378
379			`../sim/test_rx.txt`
380			`ASCII`
381			`false`
382
383			`false`
384
385			`Expected values for the receiver`
386
387
388
389			`vhdlSource`
390			`vcom`
391			`-check_synthesis`
392			`false`
393
394			`../../../../ip.hwp.storage/fifos`
395			`../../../../ip.hwp.storage/fifos/multi_clk/vhd`
396			`../../../hibi/3.0/vhd`
397
398
399
400
401
402			`IP`
403			`HW`
404			`Fixed`
405
406
407
408