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lanttu |
-------------------------------------------------------------------------------
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-- Title : A block which sends data to HIBI ver 2 and 3
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-- Project : Nocbench & Funbase
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-------------------------------------------------------------------------------
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-- File : basic_tester_tx.vhd
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-- Author : ege
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-- Created : 2010-03-24
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-- Last update: 2012-02-06
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-- Description: Reads ASCII file where each line describes transfer of 1 word.
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-- Each transfers needs 4 hexadecimal parameters:
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-- - delay (clock cycles) after previous tx
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-- - dst address
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-- - data value
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-- - command
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--
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- April 2010 1.0 ege First version
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use ieee.std_logic_textio.all; -- 2010-10-06 for hread
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use work.basic_tester_pkg.all; -- read_conf_file()
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entity basic_tester_tx is
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generic (
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conf_file_g : string := "";
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comm_width_g : integer := 5;
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data_width_g : integer := 0
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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done_out : out std_logic; -- if this unit has finished
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-- HIBI wrapper ports
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agent_av_out : out std_logic;
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agent_data_out : out std_logic_vector (data_width_g-1 downto 0);
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agent_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
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agent_we_out : out std_logic;
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agent_full_in : in std_logic;
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agent_one_p_in : in std_logic
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);
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end basic_tester_tx;
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architecture rtl of basic_tester_tx is
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-- State machine
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type control_states is (read_conf, wait_sending, wr_addr, wr_data, finish);
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signal curr_state_r : control_states := read_conf;
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signal delay_r : integer; -- Counter
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-- Registers may be reset to 'Z' to 'X' so that reset state is clearly
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-- distinguished from active state. Using dbg_level_c+Rst_Value array, the
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-- rst value may be easily set to '0' for synthesis.
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constant dbg_level_c : integer range 0 to 3 := 0; -- 0= no debug
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constant rst_val_arr_c : std_logic_vector (6 downto 0) :=
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'X' & 'Z' & 'X' & 'Z' & 'X' & 'Z' & '0';
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-- Right now gives a lot of warnings when other than 0
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begin -- rtl
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main : process (clk, rst_n)
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file conf_data_file : text open read_mode is conf_file_g;
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variable delay_v : integer;
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variable dst_ag_v : integer;
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variable data_val_v : integer;
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variable cmd_v : integer;
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begin -- process main
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if rst_n = '0' then -- asynchronous reset (active low)
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curr_state_r <= read_conf;
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agent_av_out <= '0';
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agent_data_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_comm_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_we_out <= '0';
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done_out <= '0';
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delay_r <= 0;
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delay_v := 0;
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dst_ag_v := 0;
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data_val_v := 0;
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cmd_v := 0;
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elsif clk'event and clk = '1' then -- rising clock edge
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case curr_state_r is
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when read_conf =>
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if agent_full_in = '0' then
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-- Read next transfer from file if FIFO has space
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-- and the whole file has not yet been read
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if endfile(conf_data_file) then
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curr_state_r <= finish;
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assert false report "End of the configuration file reached"
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severity note;
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else
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read_conf_file (
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delay => delay_v,
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dest_agent_n => dst_ag_v,
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value => data_val_v,
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cmd => cmd_v,
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conf_dat => conf_data_file);
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-- report "delay = " & integer'image(delay_v)
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-- & ", dst = " & integer'image(dst_ag_v)
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-- & ", value = " & integer'image(data_val_v)
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-- & ", cmd = " & integer'image(cmd_v);
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-- FSM causes few empty cycles, compensate by
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-- decrementing delay_v
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delay_v := delay_v -1;
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if cmd_v = -1 then
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cmd_v := 2; --use write as default
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end if;
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if delay_v < 1 then
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-- Start sending directly
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if dst_ag_v = 0 then
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curr_state_r <= wr_data;
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else
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curr_state_r <= wr_addr;
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end if;
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else
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curr_state_r <= wait_sending;
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end if; -- delay_v
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end if; -- endfile
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agent_av_out <= '0';
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agent_data_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_comm_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_we_out <= '0';
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delay_r <= delay_v;
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else
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-- Keep the old values
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-- i.e. either the reset values or keep sending
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curr_state_r <= read_conf;
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end if;
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when wait_sending =>
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-- Wait for a given num of cycles before sending
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delay_r <= delay_r-1;
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if delay_r < 2 then
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if dst_ag_v = 0 then
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-- Skip the address and send data directly
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curr_state_r <= wr_data;
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else
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curr_state_r <= wr_addr;
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end if;
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else
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curr_state_r <= wait_sending;
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end if;
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when wr_addr =>
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if agent_full_in = '0' then
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-- Write the address if there is room in HIBI's tx FIFO
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agent_av_out <= '1';
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agent_data_out <= std_logic_vector (to_signed(dst_ag_v, data_width_g));
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agent_comm_out <= std_logic_vector (to_signed(cmd_v, comm_width_g));
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agent_we_out <= '1';
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curr_state_r <= wr_data;
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else
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-- Don't start yet, wait that there is space in FIFO
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agent_av_out <= '0';
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agent_data_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_comm_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_we_out <= '0';
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curr_state_r <= wr_addr;
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end if;
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when wr_data =>
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if agent_full_in = '0' then
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-- Write the requested data value if there is
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-- room in HIBI's tx FIFO
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agent_av_out <= '0';
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agent_data_out <= std_logic_vector (to_signed(data_val_v, data_width_g));
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agent_comm_out <= std_logic_vector (to_signed(cmd_v, comm_width_g));
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agent_we_out <= '1';
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curr_state_r <= read_conf;
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else
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-- Keep the old values (=adst ddress) and stay in this state
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curr_state_r <= wr_data;
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end if;
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when finish =>
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-- Notify that we're done.
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done_out <= '1';
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agent_av_out <= '0';
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agent_data_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_comm_out <= (others => rst_val_arr_c(dbg_level_c*1));
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agent_we_out <= '0';
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when others => null;
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end case; -- curr_state_r
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end if; -- rst_n/clk'event
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end process main;
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end rtl;
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