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-------------------------------------------------------------------------------
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-- Title : Simple tester for crossbar
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-- Project :
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-------------------------------------------------------------------------------
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-- File : simple_test_crossbar.vhd
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-- Author : Lasse Lehtonen
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-- Company :
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-- Created : 2011-08-12
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-- Last update: 2011-08-15
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-- Platform :
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2011
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--
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-- This file is part of Transaction Generator.
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--
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-- Transaction Generator is free software: you can redistribute it and/or modify
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-- it under the terms of the Lesser GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Transaction Generator is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- Lesser GNU General Public License for more details.
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--
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-- You should have received a copy of the Lesser GNU General Public License
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-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2011-08-12 1.0 lehton87 Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity simple_test_crossbar is
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end simple_test_crossbar;
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architecture tb of simple_test_crossbar is
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-----------------------------------------------------------------------------
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-- CONSTANTS
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-----------------------------------------------------------------------------
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-- generics
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constant pkt_switch_en_c : integer := 1;
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constant n_ag_c : integer := 6;
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constant stfwd_en_c : integer := 0;
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constant data_width_c : integer := 32;
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constant addr_width_c : integer := 32;
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constant packet_length_c : integer := 6;
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constant tx_len_width_c : integer := 8;
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constant timeout_c : integer := 4;
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constant fill_packet_c : integer := 0;
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constant lut_en_c : integer := 0;
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constant net_type_c : integer := 0;
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constant len_flit_en_c : integer := 1;
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constant oaddr_flit_en_c : integer := 0;
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constant status_en_c : integer := 0;
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constant fifo_depth_c : integer := 8;
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constant net_freq_c : integer := 1;
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constant ip_freq_c : integer := 2;
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constant max_send_c : integer := 0; -- 0 = inf
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-- clock generation
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constant noc_cycle_time_c : time := 4 ns;
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constant ip_cycle_time_c : time := 2 ns;
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-----------------------------------------------------------------------------
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-- SIGNALS
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-----------------------------------------------------------------------------
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signal clk_noc : std_logic := '1';
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signal clk_ip : std_logic := '1';
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signal rst_n : std_logic := '0';
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signal rx_av : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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signal rx_data : std_logic_vector(n_ag_c*data_width_c-1 downto 0)
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:= (others => '0');
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signal we : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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signal txlen : std_logic_vector(n_ag_c*tx_len_width_c-1 downto 0)
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:= (others => '0');
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signal full : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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signal full_r : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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signal rx_empty : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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signal tx_av : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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signal tx_data : std_logic_vector(n_ag_c*data_width_c-1 downto 0)
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:= (others => '0');
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signal re : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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signal tx_empty : std_logic_vector(n_ag_c-1 downto 0)
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:= (others => '0');
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begin -- tb
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clk_noc <= not clk_noc after noc_cycle_time_c;
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clk_ip <= not clk_ip after ip_cycle_time_c;
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rst_n <= '1' after 20 ns;
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i_crossbar_with_pkt_codec_top : entity work.crossbar_with_pkt_codec_top
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generic map (
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pkt_switch_en_g => pkt_switch_en_c,
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n_ag_g => n_ag_c,
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stfwd_en_g => stfwd_en_c,
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data_width_g => data_width_c,
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addr_width_g => addr_width_c,
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packet_length_g => packet_length_c,
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tx_len_width_g => tx_len_width_c,
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timeout_g => timeout_c,
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fill_packet_g => fill_packet_c,
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lut_en_g => lut_en_c,
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len_flit_en_g => len_flit_en_c,
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oaddr_flit_en_g => oaddr_flit_en_c,
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status_en_g => status_en_c,
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max_send_g => max_send_c,
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fifo_depth_g => fifo_depth_c,
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net_freq_g => net_freq_c,
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ip_freq_g => ip_freq_c)
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port map (
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clk_net => clk_noc,
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clk_ip => clk_ip,
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rst_n => rst_n,
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tx_av_in => tx_av,
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tx_data_in => tx_data,
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tx_we_in => we,
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tx_txlen_in => txlen,
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tx_full_out => full,
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tx_empty_out => tx_empty,
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rx_av_out => rx_av,
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rx_data_out => rx_data,
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rx_re_in => re,
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rx_empty_out => rx_empty);
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basic_test_tx_1 : entity work.basic_test_tx
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generic map (
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conf_file_g => "tx_file.txt",
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comm_width_g => 2,
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data_width_g => data_width_c)
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port map (
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clk => clk_ip,
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rst_n => rst_n,
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done_out => open,
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agent_av_out => tx_av(0),
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agent_data_out => tx_data(data_width_c-1 downto 0),
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agent_comm_out => open,
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agent_we_out => we(0),
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agent_full_in => full(0),
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agent_one_p_in => '0');
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basic_test_rx_1 : entity work.basic_test_rx
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generic map (
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conf_file_g => "rx_file.txt",
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comm_width_g => 2,
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data_width_g => data_width_c)
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port map (
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clk => clk_ip,
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rst_n => rst_n,
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done_out => open,
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agent_av_in => rx_av(5),
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agent_data_in => rx_data(6*data_width_c-1 downto 5*data_width_c),
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agent_comm_in => "00",
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agent_re_out => re(5),
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agent_empty_in => rx_empty(5),
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agent_one_d_in => '0');
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end tb;
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